/*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
- UINT_32 reserved : 25; ///< Reserved bits for future use
+ UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility
+ UINT_32 nonPower2MemConfig : 1; ///< Physical video memory size is not power of 2
+ UINT_32 reserved : 23; ///< Reserved bits for future use
};
UINT_32 value;
///< CI registers-------------------------------------------------
const UINT_32* pMacroTileConfig; ///< Global macro tile mode table
UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig
-
- ///< GFX9 HW parameters
- UINT_32 blockVarSizeLog2; ///< SW_VAR_* block size
} ADDR_REGISTER_VALUE;
/**
/**
****************************************************************************************************
-* ADDR_GET_MAX_ALINGMENTS_OUTPUT
+* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
*
* @brief
* Output structure of AddrGetMaxAlignments
****************************************************************************************************
*/
-typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
+typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_32 baseAlign; ///< Maximum base alignment in bytes
-} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
+} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;
/**
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
ADDR_HANDLE hLib,
- ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
+ ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
/**
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
ADDR_HANDLE hLib,
- ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
+ ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
/**
****************************************************************************************************
UINT_32 size; ///< Size of this structure in bytes
ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
- ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
AddrResourceType resourceType; ///< Color surface type
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
UINT_32 unalignedWidth; ///< Color surface original width
UINT_32 unalignedHeight; ///< Color surface original height
UINT_32 numSlices; ///< Number of slices of color buffer
+ UINT_32 numMipLevels; ///< Number of mip levels
+ UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
+ /// it should be number of mip levels
} ADDR2_COMPUTE_CMASK_INFO_INPUT;
/**
UINT_32 metaBlkWidth; ///< Meta block width
UINT_32 metaBlkHeight; ///< Meta block height
- UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
+ UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
+
+ ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information
} ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
/**
UINT_32 slice; ///< Index of slices
ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
- ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
AddrResourceType resourceType; ///< Color surface type
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
- ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
AddrResourceType resourceType; ///< Color surface type
AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
UINT_32 size; ///< Size of this structure in bytes
ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags
- ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
AddrResourceType resourceType; ///< Color surface type
AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
UINT_32 bpp; ///< bits per pixel
UINT_32 mipId; ///< mipmap level id
ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
- ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
AddrResourceType resourceType; ///< Color surface type
AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
UINT_32 bpp; ///< Color surface bits per pixel
- UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
- UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
UINT_32 numSlices; ///< Color surface original slices (of mip0)
UINT_32 numMipLevels; ///< Color surface mipmap levels
UINT_32 numFrags; ///< Color surface fragment number
UINT_32 pipeXor; ///< pipe Xor setting
+ UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch
+ UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height
+ UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth
+ UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight
+ UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth
+ UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth
+ UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight
+ UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth
+ UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize
} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
/**
{
struct
{
- UINT_32 micro : 1; // 256B block for 2D resource
- UINT_32 macro4KB : 1; // 4KB for 2D/3D resource
- UINT_32 macro64KB : 1; // 64KB for 2D/3D resource
- UINT_32 var : 1; // VAR block
- UINT_32 linear : 1; // Linear block
- UINT_32 reserved : 27;
+ UINT_32 micro : 1; // 256B block for 2D resource
+ UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource
+ UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource
+ UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource
+ UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource
+ UINT_32 var : 1; // VAR block
+ UINT_32 linear : 1; // Linear block
+ UINT_32 reserved : 25;
};
UINT_32 value;
{
struct
{
- UINT_32 swLinear : 1;
- UINT_32 sw256B_S : 1;
- UINT_32 sw256B_D : 1;
- UINT_32 sw256B_R : 1;
- UINT_32 sw4KB_Z : 1;
- UINT_32 sw4KB_S : 1;
- UINT_32 sw4KB_D : 1;
- UINT_32 sw4KB_R : 1;
- UINT_32 sw64KB_Z : 1;
- UINT_32 sw64KB_S : 1;
- UINT_32 sw64KB_D : 1;
- UINT_32 sw64KB_R : 1;
- UINT_32 swVar_Z : 1;
- UINT_32 swVar_S : 1;
- UINT_32 swVar_D : 1;
- UINT_32 swVar_R : 1;
- UINT_32 sw64KB_Z_T : 1;
- UINT_32 sw64KB_S_T : 1;
- UINT_32 sw64KB_D_T : 1;
- UINT_32 sw64KB_R_T : 1;
- UINT_32 sw4KB_Z_X : 1;
- UINT_32 sw4KB_S_X : 1;
- UINT_32 sw4KB_D_X : 1;
- UINT_32 sw4KB_R_X : 1;
- UINT_32 sw64KB_Z_X : 1;
- UINT_32 sw64KB_S_X : 1;
- UINT_32 sw64KB_D_X : 1;
- UINT_32 sw64KB_R_X : 1;
- UINT_32 swVar_Z_X : 1;
- UINT_32 swVar_S_X : 1;
- UINT_32 swVar_D_X : 1;
- UINT_32 swVar_R_X : 1;
+ UINT_32 swLinear : 1;
+ UINT_32 sw256B_S : 1;
+ UINT_32 sw256B_D : 1;
+ UINT_32 sw256B_R : 1;
+ UINT_32 sw4KB_Z : 1;
+ UINT_32 sw4KB_S : 1;
+ UINT_32 sw4KB_D : 1;
+ UINT_32 sw4KB_R : 1;
+ UINT_32 sw64KB_Z : 1;
+ UINT_32 sw64KB_S : 1;
+ UINT_32 sw64KB_D : 1;
+ UINT_32 sw64KB_R : 1;
+ UINT_32 swReserved0 : 1;
+ UINT_32 swReserved1 : 1;
+ UINT_32 swReserved2 : 1;
+ UINT_32 swReserved3 : 1;
+ UINT_32 sw64KB_Z_T : 1;
+ UINT_32 sw64KB_S_T : 1;
+ UINT_32 sw64KB_D_T : 1;
+ UINT_32 sw64KB_R_T : 1;
+ UINT_32 sw4KB_Z_X : 1;
+ UINT_32 sw4KB_S_X : 1;
+ UINT_32 sw4KB_D_X : 1;
+ UINT_32 sw4KB_R_X : 1;
+ UINT_32 sw64KB_Z_X : 1;
+ UINT_32 sw64KB_S_X : 1;
+ UINT_32 sw64KB_D_X : 1;
+ UINT_32 sw64KB_R_X : 1;
+ UINT_32 swVar_Z_X : 1;
+ UINT_32 swReserved4 : 1;
+ UINT_32 swReserved5 : 1;
+ UINT_32 swVar_R_X : 1;
};
UINT_32 value;
projects / mesa.git / blobdiff