amd/addrlib: update to the latest version

[mesa.git] / src / amd / addrlib / inc / addrtypes.h

diff --git a/src/amd/addrlib/inc/addrtypes.h b/src/amd/addrlib/inc/addrtypes.h
index 36e342f31760a69ab5d1fc9406b9a26b9167ccea..7d8ca9266781a087dbfbec3ab9d954d5103d17c4 100644 (file)
--- a/src/amd/addrlib/inc/addrtypes.h
+++ b/src/amd/addrlib/inc/addrtypes.h
@@ -90,11 +90,7 @@ typedef int            INT;
     #if defined(BRAHMA_ARM)
         #define ADDR_FASTCALL
     #elif defined(__GNUC__)
-        #if defined(__i386__)
-            #define ADDR_FASTCALL __attribute__((regparm(0)))
-        #else
-            #define ADDR_FASTCALL
-        #endif
+        #define ADDR_FASTCALL __attribute__((regparm(0)))
     #else
         #define ADDR_FASTCALL __fastcall
     #endif
@@ -203,22 +199,32 @@ typedef enum _AddrTileMode
 /**
 ****************************************************************************************************
 * @brief
-*   Neutral enums that define swizzle modes for Gfx9 ASIC
+*   Neutral enums that define swizzle modes for Gfx9+ ASIC
 * @note
 *
-*   ADDR_SW_LINEAR linear aligned addressing mode, for 1D/2D/3D resouce
-*   ADDR_SW_256B_* addressing block aligned size is 256B, for 2D/3D resouce
-*   ADDR_SW_4KB_*  addressing block aligned size is 4KB, for 2D/3D resouce
-*   ADDR_SW_64KB_* addressing block aligned size is 64KB, for 2D/3D resouce
-*   ADDR_SW_VAR_*  addressing block aligned size is ASIC specific, for 2D/3D resouce
+*   ADDR_SW_LINEAR linear aligned addressing mode, for 1D/2D/3D resource
+*   ADDR_SW_256B_* addressing block aligned size is 256B, for 2D/3D resource
+*   ADDR_SW_4KB_*  addressing block aligned size is 4KB, for 2D/3D resource
+*   ADDR_SW_64KB_* addressing block aligned size is 64KB, for 2D/3D resource
 *
-*   ADDR_SW_*_Z    For 2D resouce, represents Z-order swizzle mode for depth/stencil/FMask
-                   For 3D resouce, represents a swizzle mode similar to legacy thick tile mode
-*   ADDR_SW_*_S    represents standard swizzle mode defined by MS
-*   ADDR_SW_*_D    For 2D resouce, represents a swizzle mode for displayable resource
-*                  For 3D resouce, represents a swizzle mode which places each slice in order & pixel
+*   ADDR_SW_*_Z    For GFX9:
+                   - for 2D resource, represents Z-order swizzle mode for depth/stencil/FMask
+                   - for 3D resource, represents a swizzle mode similar to legacy thick tile mode
+                   For GFX10:
+                   - represents Z-order swizzle mode for depth/stencil/FMask
+*   ADDR_SW_*_S    For GFX9+:
+                   - represents standard swizzle mode defined by MS
+*   ADDR_SW_*_D    For GFX9:
+                   - for 2D resource, represents a swizzle mode for displayable resource
+*                  - for 3D resource, represents a swizzle mode which places each slice in order & pixel
+                   For GFX10:
+                   - for 2D resource, represents a swizzle mode for displayable resource
+                   - for 3D resource, represents a swizzle mode similar to legacy thick tile mode
                    within slice is placed as 2D ADDR_SW_*_S. Don't use this combination if possible!
-*   ADDR_SW_*_R    For 2D resouce only, represents a swizzle mode for rotated displayable resource
+*   ADDR_SW_*_R    For GFX9:
+                   - 2D resource only, represents a swizzle mode for rotated displayable resource
+                   For GFX10:
+                   - represents a swizzle mode for render target resource
 *
 ****************************************************************************************************
 */
@@ -236,10 +242,10 @@ typedef enum _AddrSwizzleMode
     ADDR_SW_64KB_S          = 9,
     ADDR_SW_64KB_D          = 10,
     ADDR_SW_64KB_R          = 11,
-    ADDR_SW_VAR_Z           = 12,
-    ADDR_SW_VAR_S           = 13,
-    ADDR_SW_VAR_D           = 14,
-    ADDR_SW_VAR_R           = 15,
+    ADDR_SW_RESERVED0       = 12,
+    ADDR_SW_RESERVED1       = 13,
+    ADDR_SW_RESERVED2       = 14,
+    ADDR_SW_RESERVED3       = 15,
     ADDR_SW_64KB_Z_T        = 16,
     ADDR_SW_64KB_S_T        = 17,
     ADDR_SW_64KB_D_T        = 18,
@@ -253,17 +259,11 @@ typedef enum _AddrSwizzleMode
     ADDR_SW_64KB_D_X        = 26,
     ADDR_SW_64KB_R_X        = 27,
     ADDR_SW_VAR_Z_X         = 28,
-    ADDR_SW_VAR_S_X         = 29,
-    ADDR_SW_VAR_D_X         = 30,
+    ADDR_SW_RESERVED4       = 29,
+    ADDR_SW_RESERVED5       = 30,
     ADDR_SW_VAR_R_X         = 31,
     ADDR_SW_LINEAR_GENERAL  = 32,
     ADDR_SW_MAX_TYPE        = 33,
-
-    // Used for represent block with identical size
-    ADDR_SW_256B            = ADDR_SW_256B_S,
-    ADDR_SW_4KB             = ADDR_SW_4KB_S_X,
-    ADDR_SW_64KB            = ADDR_SW_64KB_S_X,
-    ADDR_SW_VAR             = ADDR_SW_VAR_S_X,
 } AddrSwizzleMode;
 
 /**
@@ -316,7 +316,9 @@ typedef enum _AddrSwType
     ADDR_SW_Z  = 0,   // Resource basic swizzle mode is ZOrder
     ADDR_SW_S  = 1,   // Resource basic swizzle mode is Standard
     ADDR_SW_D  = 2,   // Resource basic swizzle mode is Display
-    ADDR_SW_R  = 3,   // Resource basic swizzle mode is Rotated
+    ADDR_SW_R  = 3,   // Resource basic swizzle mode is Rotated/Render optimized
+    ADDR_SW_L  = 4,   // Resource basic swizzle mode is Linear
+    ADDR_SW_MAX_SWTYPE
 } AddrSwType;
 
 /**