/*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
#endif
#ifndef ADDR_FASTCALL
- #if defined(BRAHMA_ARM)
- #define ADDR_FASTCALL
- #elif defined(__GNUC__)
- #if defined(__i386__)
- #define ADDR_FASTCALL __attribute__((regparm(0)))
- #else
- #define ADDR_FASTCALL
- #endif
+ #if defined(__GNUC__)
+ #define ADDR_FASTCALL __attribute__((regparm(0)))
#else
#define ADDR_FASTCALL __fastcall
#endif
#define ADDR_INLINE __inline
#endif // #if defined(__GNUC__)
-#define ADDR_API ADDR_FASTCALL //default call convention is fast call
+#if defined(__amd64__) || defined(__x86_64__) || defined(__i386__)
+ #define ADDR_API ADDR_FASTCALL // default call convention is fast call
+#else
+ #define ADDR_API
+#endif
/**
****************************************************************************************************
/**
****************************************************************************************************
* @brief
-* Neutral enums that define swizzle modes for Gfx9 ASIC
+* Neutral enums that define swizzle modes for Gfx9+ ASIC
* @note
*
-* ADDR_SW_LINEAR linear aligned addressing mode, for 1D/2D/3D resouce
-* ADDR_SW_256B_* addressing block aligned size is 256B, for 2D/3D resouce
-* ADDR_SW_4KB_* addressing block aligned size is 4KB, for 2D/3D resouce
-* ADDR_SW_64KB_* addressing block aligned size is 64KB, for 2D/3D resouce
-* ADDR_SW_VAR_* addressing block aligned size is ASIC specific, for 2D/3D resouce
+* ADDR_SW_LINEAR linear aligned addressing mode, for 1D/2D/3D resource
+* ADDR_SW_256B_* addressing block aligned size is 256B, for 2D/3D resource
+* ADDR_SW_4KB_* addressing block aligned size is 4KB, for 2D/3D resource
+* ADDR_SW_64KB_* addressing block aligned size is 64KB, for 2D/3D resource
*
-* ADDR_SW_*_Z For 2D resouce, represents Z-order swizzle mode for depth/stencil/FMask
- For 3D resouce, represents a swizzle mode similar to legacy thick tile mode
-* ADDR_SW_*_S represents standard swizzle mode defined by MS
-* ADDR_SW_*_D For 2D resouce, represents a swizzle mode for displayable resource
-* For 3D resouce, represents a swizzle mode which places each slice in order & pixel
+* ADDR_SW_*_Z For GFX9:
+ - for 2D resource, represents Z-order swizzle mode for depth/stencil/FMask
+ - for 3D resource, represents a swizzle mode similar to legacy thick tile mode
+ For GFX10:
+ - represents Z-order swizzle mode for depth/stencil/FMask
+* ADDR_SW_*_S For GFX9+:
+ - represents standard swizzle mode defined by MS
+* ADDR_SW_*_D For GFX9:
+ - for 2D resource, represents a swizzle mode for displayable resource
+* - for 3D resource, represents a swizzle mode which places each slice in order & pixel
+ For GFX10:
+ - for 2D resource, represents a swizzle mode for displayable resource
+ - for 3D resource, represents a swizzle mode similar to legacy thick tile mode
within slice is placed as 2D ADDR_SW_*_S. Don't use this combination if possible!
-* ADDR_SW_*_R For 2D resouce only, represents a swizzle mode for rotated displayable resource
+* ADDR_SW_*_R For GFX9:
+ - 2D resource only, represents a swizzle mode for rotated displayable resource
+ For GFX10:
+ - represents a swizzle mode for render target resource
*
****************************************************************************************************
*/
ADDR_SW_64KB_S = 9,
ADDR_SW_64KB_D = 10,
ADDR_SW_64KB_R = 11,
- ADDR_SW_VAR_Z = 12,
- ADDR_SW_VAR_S = 13,
- ADDR_SW_VAR_D = 14,
- ADDR_SW_VAR_R = 15,
+ ADDR_SW_RESERVED0 = 12,
+ ADDR_SW_RESERVED1 = 13,
+ ADDR_SW_RESERVED2 = 14,
+ ADDR_SW_RESERVED3 = 15,
ADDR_SW_64KB_Z_T = 16,
ADDR_SW_64KB_S_T = 17,
ADDR_SW_64KB_D_T = 18,
ADDR_SW_64KB_D_X = 26,
ADDR_SW_64KB_R_X = 27,
ADDR_SW_VAR_Z_X = 28,
- ADDR_SW_VAR_S_X = 29,
- ADDR_SW_VAR_D_X = 30,
+ ADDR_SW_RESERVED4 = 29,
+ ADDR_SW_RESERVED5 = 30,
ADDR_SW_VAR_R_X = 31,
ADDR_SW_LINEAR_GENERAL = 32,
ADDR_SW_MAX_TYPE = 33,
-
- // Used for represent block with identical size
- ADDR_SW_256B = ADDR_SW_256B_S,
- ADDR_SW_4KB = ADDR_SW_4KB_S_X,
- ADDR_SW_64KB = ADDR_SW_64KB_S_X,
- ADDR_SW_VAR = ADDR_SW_VAR_S_X,
} AddrSwizzleMode;
/**
ADDR_SW_Z = 0, // Resource basic swizzle mode is ZOrder
ADDR_SW_S = 1, // Resource basic swizzle mode is Standard
ADDR_SW_D = 2, // Resource basic swizzle mode is Display
- ADDR_SW_R = 3, // Resource basic swizzle mode is Rotated
+ ADDR_SW_R = 3, // Resource basic swizzle mode is Rotated/Render optimized
+ ADDR_SW_L = 4, // Resource basic swizzle mode is Linear
+ ADDR_SW_MAX_SWTYPE
} AddrSwType;
/**
*/
typedef enum _AddrPipeCfg
{
- ADDR_PIPECFG_INVALID = 0,
- ADDR_PIPECFG_P2 = 1, /// 2 pipes,
- ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes,
- ADDR_PIPECFG_P4_16x16 = 6,
- ADDR_PIPECFG_P4_16x32 = 7,
- ADDR_PIPECFG_P4_32x32 = 8,
- ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes
- ADDR_PIPECFG_P8_16x32_8x16 = 10,
- ADDR_PIPECFG_P8_32x32_8x16 = 11,
- ADDR_PIPECFG_P8_16x32_16x16 = 12,
- ADDR_PIPECFG_P8_32x32_16x16 = 13,
- ADDR_PIPECFG_P8_32x32_16x32 = 14,
- ADDR_PIPECFG_P8_32x64_32x32 = 15,
- ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
- ADDR_PIPECFG_P16_32x32_16x16 = 18,
- ADDR_PIPECFG_RESERVED = 19, /// reserved for internal use
- ADDR_PIPECFG_MAX = 20,
+ ADDR_PIPECFG_INVALID = 0,
+ ADDR_PIPECFG_P2 = 1, /// 2 pipes,
+ ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes,
+ ADDR_PIPECFG_P4_16x16 = 6,
+ ADDR_PIPECFG_P4_16x32 = 7,
+ ADDR_PIPECFG_P4_32x32 = 8,
+ ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes
+ ADDR_PIPECFG_P8_16x32_8x16 = 10,
+ ADDR_PIPECFG_P8_32x32_8x16 = 11,
+ ADDR_PIPECFG_P8_16x32_16x16 = 12,
+ ADDR_PIPECFG_P8_32x32_16x16 = 13,
+ ADDR_PIPECFG_P8_32x32_16x32 = 14,
+ ADDR_PIPECFG_P8_32x64_32x32 = 15,
+ ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
+ ADDR_PIPECFG_P16_32x32_16x16 = 18,
+ ADDR_PIPECFG_UNUSED = 19,
+ ADDR_PIPECFG_MAX = 20,
} AddrPipeCfg;
/**
projects / mesa.git / blobdiff