ac: add LLVM code for triangle culling

[mesa.git] / src / amd / common / ac_surface.h

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 71f320af8eeb0e01f8383ac8cde9abb534239f15..08aac94d3a942db1808889b355fc3eb95d59446f 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -27,6 +27,7 @@
 #define AC_SURFACE_H
 
 #include <stdint.h>
+#include <stdbool.h>
 
 #include "amd_family.h"
 
@@ -68,6 +69,7 @@ enum radeon_micro_mode {
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
+#define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
 
 struct legacy_surf_level {
     uint64_t                    offset;
@@ -79,6 +81,13 @@ struct legacy_surf_level {
     enum radeon_surf_mode       mode:2;
 };
 
+struct legacy_surf_fmask {
+    unsigned slice_tile_max; /* max 4M */
+    uint8_t tiling_index;    /* max 31 */
+    uint8_t bankh;           /* max 8 */
+    uint16_t pitch_in_pixels;
+};
+
 struct legacy_surf_layout {
     unsigned                    bankw:4;  /* max 8 */
     unsigned                    bankh:4;  /* max 8 */
@@ -101,6 +110,8 @@ struct legacy_surf_layout {
     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
+    struct legacy_surf_fmask    fmask;
+    unsigned                    cmask_slice_tile_max;
 };
 
 /* Same as addrlib - AddrResourceType. */
@@ -139,16 +150,19 @@ struct gfx9_surf_layout {
     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 
-    uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
-
     uint64_t                    stencil_offset; /* separate stencil */
-    uint64_t                    fmask_size;
-    uint64_t                    cmask_size;
-
-    uint32_t                    fmask_alignment;
-    uint32_t                    cmask_alignment;
 
-    uint8_t                     fmask_tile_swizzle;
+    /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
+     * The 3D engine doesn't support that layout except for chips with 1 RB.
+     * All other chips must set rb_aligned=1.
+     * A compute shader needs to convert from aligned DCC to unaligned.
+     */
+    uint32_t                    display_dcc_size;
+    uint32_t                    display_dcc_alignment;
+    uint16_t                    display_dcc_pitch_max;  /* (mip chain pitch - 1) */
+    bool                        dcc_retile_use_uint16; /* if all values fit into uint16_t */
+    uint32_t                    dcc_retile_num_elements;
+    uint32_t                    *dcc_retile_map;
 };
 
 struct radeon_surf {
@@ -188,20 +202,26 @@ struct radeon_surf {
      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
      */
     uint8_t                     tile_swizzle;
+    uint8_t                     fmask_tile_swizzle;
 
     uint64_t                    surf_size;
+    uint64_t                    fmask_size;
+    uint32_t                    surf_alignment;
+    uint32_t                    fmask_alignment;
+
     /* DCC and HTILE are very small. */
     uint32_t                    dcc_size;
-    uint32_t                    htile_size;
+    uint32_t                    dcc_alignment;
 
+    uint32_t                    htile_size;
     uint32_t                    htile_slice_size;
-
-    uint32_t                    surf_alignment;
-    uint32_t                    dcc_alignment;
     uint32_t                    htile_alignment;
 
+    uint32_t                    cmask_size;
+    uint32_t                    cmask_alignment;
+
     union {
-        /* R600-VI return values.
+        /* Return values for GFX8 and older.
          *
          * Some of them can be set by the caller if certain parameters are
          * desirable. The allocator will try to obey them.
@@ -217,11 +237,13 @@ struct ac_surf_info {
        uint32_t width;
        uint32_t height;
        uint32_t depth;
-       uint8_t samples;
+       uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
+       uint8_t storage_samples; /* For color: allocated samples */
        uint8_t levels;
+       uint8_t num_channels; /* heuristic for displayability */
        uint16_t array_size;
        uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
-       uint32_t *fmask_surf_index; /* GFX9+ */
+       uint32_t *fmask_surf_index;
 };
 
 struct ac_surf_config {
@@ -239,6 +261,10 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
                       enum radeon_surf_mode mode,
                       struct radeon_surf *surf);
 
+void ac_compute_cmask(const struct radeon_info *info,
+                     const struct ac_surf_config *config,
+                     struct radeon_surf *surf);
+
 #ifdef __cplusplus
 }
 #endif