python: Use the print function

[mesa.git] / src / amd / common / sid_tables.py

diff --git a/src/amd/common/sid_tables.py b/src/amd/common/sid_tables.py
index ca90f82535d962e48a82807210a874e0095d24f6..421c2a13352a4b70ed9c619041b96a88bb17458d 100644 (file)
--- a/src/amd/common/sid_tables.py
+++ b/src/amd/common/sid_tables.py
@@ -1,3 +1,4 @@
+from __future__ import print_function
 
 CopyRight = '''
 /*
@@ -333,10 +334,10 @@ def write_tables(asics, packets):
     strings_offsets = IntTable("int")
     fields = FieldTable()
 
-    print '/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */'
-    print
-    print CopyRight.strip()
-    print '''
+    print('/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */')
+    print()
+    print(CopyRight.strip())
+    print('''
 #ifndef SID_TABLES_H
 #define SID_TABLES_H
 
@@ -358,17 +359,17 @@ struct si_packet3 {
         unsigned name_offset;
         unsigned op;
 };
-'''
+''')
 
-    print 'static const struct si_packet3 packet3_table[] = {'
+    print('static const struct si_packet3 packet3_table[] = {')
     for pkt in packets:
-        print '\t{%s, %s},' % (strings.add(pkt[5:]), pkt)
-    print '};'
-    print
+        print('\t{%s, %s},' % (strings.add(pkt[5:]), pkt))
+    print('};')
+    print()
 
     regs = {}
     for asic in asics:
-        print 'static const struct si_reg %s_reg_table[] = {' % (asic.name)
+        print('static const struct si_reg %s_reg_table[] = {' % (asic.name))
         for reg in asic.registers:
             # Only output a register that was changed or added relative to
             # the previous generation
@@ -377,27 +378,27 @@ struct si_packet3 {
                 continue
 
             if len(reg.fields):
-                print '\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
-                    len(reg.fields), fields.add(reg.fields))
+                print('\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
+                    len(reg.fields), fields.add(reg.fields)))
             else:
-                print '\t{%s, %s},' % (strings.add(reg.name), reg.r_name)
+                print('\t{%s, %s},' % (strings.add(reg.name), reg.r_name))
 
             regs[reg.r_name] = reg
-        print '};'
-        print
+        print('};')
+        print()
 
     fields.emit(sys.stdout, strings, strings_offsets)
 
-    print
+    print()
 
     strings.emit(sys.stdout, "sid_strings")
 
-    print
+    print()
 
     strings_offsets.emit(sys.stdout, "sid_strings_offsets")
 
-    print
-    print '#endif'
+    print()
+    print('#endif')
 
 
 def main():