struct mad_info {
aco_ptr<Instruction> add_instr;
uint32_t mul_temp_id;
- uint32_t literal_idx;
- bool needs_vop3;
+ uint16_t literal_idx;
bool check_literal;
- mad_info(aco_ptr<Instruction> instr, uint32_t id, bool vop3)
- : add_instr(std::move(instr)), mul_temp_id(id), needs_vop3(vop3), check_literal(false) {}
+ mad_info(aco_ptr<Instruction> instr, uint32_t id)
+ : add_instr(std::move(instr)), mul_temp_id(id), check_literal(false) {}
};
enum Label {
label_vec = 1 << 0,
- label_constant = 1 << 1,
+ label_constant_32bit = 1 << 1,
+ /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
+ * 32-bit operations but this shouldn't cause any issues because we don't
+ * look through any conversions */
label_abs = 1 << 2,
label_neg = 1 << 3,
label_mul = 1 << 4,
label_add_sub = 1 << 17,
label_bitwise = 1 << 18,
label_minmax = 1 << 19,
- label_fcmp = 1 << 20,
+ label_vopc = 1 << 20,
+ label_uniform_bool = 1 << 21,
+ label_constant_64bit = 1 << 22,
+ label_uniform_bitwise = 1 << 23,
+ label_scc_invert = 1 << 24,
+ label_vcc_hint = 1 << 25,
+ label_scc_needed = 1 << 26,
+ label_b2i = 1 << 27,
+ label_constant_16bit = 1 << 29,
};
-static constexpr uint32_t instr_labels = label_vec | label_mul | label_mad | label_omod_success | label_clamp_success | label_add_sub | label_bitwise | label_minmax | label_fcmp;
-static constexpr uint32_t temp_labels = label_abs | label_neg | label_temp | label_vcc | label_b2f;
-static constexpr uint32_t val_labels = label_constant | label_literal | label_mad;
+static constexpr uint64_t instr_labels = label_vec | label_mul | label_mad | label_omod_success | label_clamp_success |
+ label_add_sub | label_bitwise | label_uniform_bitwise | label_minmax | label_vopc;
+static constexpr uint64_t temp_labels = label_abs | label_neg | label_temp | label_vcc | label_b2f | label_uniform_bool |
+ label_omod2 | label_omod4 | label_omod5 | label_clamp | label_scc_invert | label_b2i;
+static constexpr uint32_t val_labels = label_constant_32bit | label_constant_64bit | label_constant_16bit | label_literal;
struct ssa_info {
- uint32_t val;
+ uint64_t label;
union {
+ uint32_t val;
Temp temp;
Instruction* instr;
};
- uint32_t label;
+
+ ssa_info() : label(0) {}
void add_label(Label new_label)
{
* (indicating the defining instruction), there is no need to clear
* any other instr labels. */
if (new_label & instr_labels)
- label &= ~temp_labels; /* instr and temp alias */
+ label &= ~(temp_labels | val_labels); /* instr, temp and val alias */
if (new_label & temp_labels) {
label &= ~temp_labels;
- label &= ~instr_labels; /* instr and temp alias */
+ label &= ~(instr_labels | val_labels); /* instr, temp and val alias */
}
- if (new_label & val_labels)
+ uint32_t const_labels = label_literal | label_constant_32bit | label_constant_64bit | label_constant_16bit;
+ if (new_label & const_labels) {
+ label &= ~val_labels | const_labels;
+ label &= ~(instr_labels | temp_labels); /* instr, temp and val alias */
+ } else if (new_label & val_labels) {
label &= ~val_labels;
+ label &= ~(instr_labels | temp_labels); /* instr, temp and val alias */
+ }
label |= new_label;
}
return label & label_vec;
}
- void set_constant(uint32_t constant)
+ void set_constant(chip_class chip, uint64_t constant)
{
- add_label(label_constant);
+ Operand op16((uint16_t)constant);
+ Operand op32((uint32_t)constant);
+ add_label(label_literal);
val = constant;
+
+ if (chip >= GFX8 && !op16.isLiteral())
+ add_label(label_constant_16bit);
+
+ if (!op32.isLiteral() || ((uint32_t)constant == 0x3e22f983 && chip >= GFX8))
+ add_label(label_constant_32bit);
+
+ if (constant <= 64) {
+ add_label(label_constant_64bit);
+ } else if (constant >= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
+ add_label(label_constant_64bit);
+ } else if (constant == 0x3FE0000000000000) { /* 0.5 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0xBFE0000000000000) { /* -0.5 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0x3FF0000000000000) { /* 1.0 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0xBFF0000000000000) { /* -1.0 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0x4000000000000000) { /* 2.0 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0xC000000000000000) { /* -2.0 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0x4010000000000000) { /* 4.0 */
+ add_label(label_constant_64bit);
+ } else if (constant == 0xC010000000000000) { /* -4.0 */
+ add_label(label_constant_64bit);
+ }
+
+ if (label & label_constant_64bit) {
+ val = Operand(constant).constantValue();
+ if (val != constant)
+ label &= ~(label_literal | label_constant_16bit | label_constant_32bit);
+ }
+ }
+
+ bool is_constant(unsigned bits)
+ {
+ switch (bits) {
+ case 8:
+ return label & label_literal;
+ case 16:
+ return label & label_constant_16bit;
+ case 32:
+ return label & label_constant_32bit;
+ case 64:
+ return label & label_constant_64bit;
+ }
+ return false;
}
- bool is_constant()
+ bool is_literal(unsigned bits)
{
- return label & label_constant;
+ bool is_lit = label & label_literal;
+ switch (bits) {
+ case 8:
+ return false;
+ case 16:
+ return is_lit && ~(label & label_constant_16bit);
+ case 32:
+ return is_lit && ~(label & label_constant_32bit);
+ case 64:
+ return false;
+ }
+ return false;
+ }
+
+ bool is_constant_or_literal(unsigned bits)
+ {
+ if (bits == 64)
+ return label & label_constant_64bit;
+ else
+ return label & label_literal;
}
void set_abs(Temp abs_temp)
return label & label_temp;
}
- void set_literal(uint32_t lit)
- {
- add_label(label_literal);
- val = lit;
- }
-
- bool is_literal()
- {
- return label & label_literal;
- }
-
void set_mad(Instruction* mad, uint32_t mad_info_idx)
{
add_label(label_mad);
- val = mad_info_idx;
+ mad->pass_flags = mad_info_idx;
instr = mad;
}
return label & label_mad;
}
- void set_omod2()
+ void set_omod2(Temp def)
{
add_label(label_omod2);
+ temp = def;
}
bool is_omod2()
return label & label_omod2;
}
- void set_omod4()
+ void set_omod4(Temp def)
{
add_label(label_omod4);
+ temp = def;
}
bool is_omod4()
return label & label_omod4;
}
- void set_omod5()
+ void set_omod5(Temp def)
{
add_label(label_omod5);
+ temp = def;
}
bool is_omod5()
return label & label_omod_success;
}
- void set_clamp()
+ void set_clamp(Temp def)
{
add_label(label_clamp);
+ temp = def;
}
bool is_clamp()
return label & label_vcc;
}
- bool is_constant_or_literal()
- {
- return is_constant() || is_literal();
- }
-
void set_b2f(Temp val)
{
add_label(label_b2f);
return label & label_bitwise;
}
+ void set_uniform_bitwise()
+ {
+ add_label(label_uniform_bitwise);
+ }
+
+ bool is_uniform_bitwise()
+ {
+ return label & label_uniform_bitwise;
+ }
+
void set_minmax(Instruction *minmax_instr)
{
add_label(label_minmax);
return label & label_minmax;
}
- void set_fcmp(Instruction *fcmp_instr)
+ void set_vopc(Instruction *vopc_instr)
+ {
+ add_label(label_vopc);
+ instr = vopc_instr;
+ }
+
+ bool is_vopc()
+ {
+ return label & label_vopc;
+ }
+
+ void set_scc_needed()
+ {
+ add_label(label_scc_needed);
+ }
+
+ bool is_scc_needed()
+ {
+ return label & label_scc_needed;
+ }
+
+ void set_scc_invert(Temp scc_inv)
{
- add_label(label_fcmp);
- instr = fcmp_instr;
+ add_label(label_scc_invert);
+ temp = scc_inv;
}
- bool is_fcmp()
+ bool is_scc_invert()
{
- return label & label_fcmp;
+ return label & label_scc_invert;
+ }
+
+ void set_uniform_bool(Temp uniform_bool)
+ {
+ add_label(label_uniform_bool);
+ temp = uniform_bool;
+ }
+
+ bool is_uniform_bool()
+ {
+ return label & label_uniform_bool;
+ }
+
+ void set_vcc_hint()
+ {
+ add_label(label_vcc_hint);
+ }
+
+ bool is_vcc_hint()
+ {
+ return label & label_vcc_hint;
+ }
+
+ void set_b2i(Temp val)
+ {
+ add_label(label_b2i);
+ temp = val;
+ }
+
+ bool is_b2i()
+ {
+ return label & label_b2i;
}
};
std::vector<uint16_t> uses;
};
+struct CmpInfo {
+ aco_opcode ordered;
+ aco_opcode unordered;
+ aco_opcode ordered_swapped;
+ aco_opcode unordered_swapped;
+ aco_opcode inverse;
+ aco_opcode f32;
+ unsigned size;
+};
+
+ALWAYS_INLINE bool get_cmp_info(aco_opcode op, CmpInfo *info);
+
bool can_swap_operands(aco_ptr<Instruction>& instr)
{
if (instr->operands[0].isConstant() ||
return false;
switch (instr->opcode) {
+ case aco_opcode::v_add_u32:
+ case aco_opcode::v_add_co_u32:
+ case aco_opcode::v_add_co_u32_e64:
+ case aco_opcode::v_add_i32:
+ case aco_opcode::v_add_f16:
case aco_opcode::v_add_f32:
+ case aco_opcode::v_mul_f16:
case aco_opcode::v_mul_f32:
case aco_opcode::v_or_b32:
case aco_opcode::v_and_b32:
case aco_opcode::v_xor_b32:
+ case aco_opcode::v_max_f16:
case aco_opcode::v_max_f32:
+ case aco_opcode::v_min_f16:
case aco_opcode::v_min_f32:
- case aco_opcode::v_cmp_eq_f32:
- case aco_opcode::v_cmp_lg_f32:
+ case aco_opcode::v_max_i32:
+ case aco_opcode::v_min_i32:
+ case aco_opcode::v_max_u32:
+ case aco_opcode::v_min_u32:
+ case aco_opcode::v_max_i16:
+ case aco_opcode::v_min_i16:
+ case aco_opcode::v_max_u16:
+ case aco_opcode::v_min_u16:
+ case aco_opcode::v_max_i16_e64:
+ case aco_opcode::v_min_i16_e64:
+ case aco_opcode::v_max_u16_e64:
+ case aco_opcode::v_min_u16_e64:
+ return true;
+ case aco_opcode::v_sub_f16:
+ instr->opcode = aco_opcode::v_subrev_f16;
return true;
case aco_opcode::v_sub_f32:
instr->opcode = aco_opcode::v_subrev_f32;
return true;
- case aco_opcode::v_cmp_lt_f32:
- instr->opcode = aco_opcode::v_cmp_gt_f32;
+ case aco_opcode::v_sub_co_u32:
+ instr->opcode = aco_opcode::v_subrev_co_u32;
return true;
- case aco_opcode::v_cmp_ge_f32:
- instr->opcode = aco_opcode::v_cmp_le_f32;
+ case aco_opcode::v_sub_u16:
+ instr->opcode = aco_opcode::v_subrev_u16;
return true;
- case aco_opcode::v_cmp_lt_i32:
- instr->opcode = aco_opcode::v_cmp_gt_i32;
+ case aco_opcode::v_sub_u32:
+ instr->opcode = aco_opcode::v_subrev_u32;
return true;
- default:
+ default: {
+ CmpInfo info;
+ get_cmp_info(instr->opcode, &info);
+ if (info.ordered == instr->opcode) {
+ instr->opcode = info.ordered_swapped;
+ return true;
+ }
+ if (info.unordered == instr->opcode) {
+ instr->opcode = info.unordered_swapped;
+ return true;
+ }
return false;
}
+ }
}
-bool can_use_VOP3(aco_ptr<Instruction>& instr)
+bool can_use_VOP3(opt_ctx& ctx, const aco_ptr<Instruction>& instr)
{
- if (instr->operands.size() && instr->operands[0].isLiteral())
+ if (instr->isVOP3())
+ return true;
+
+ if (instr->operands.size() && instr->operands[0].isLiteral() && ctx.program->chip_class < GFX10)
return false;
if (instr->isDPP() || instr->isSDWA())
return instr->opcode != aco_opcode::v_madmk_f32 &&
instr->opcode != aco_opcode::v_madak_f32 &&
instr->opcode != aco_opcode::v_madmk_f16 &&
- instr->opcode != aco_opcode::v_madak_f16;
+ instr->opcode != aco_opcode::v_madak_f16 &&
+ instr->opcode != aco_opcode::v_fmamk_f32 &&
+ instr->opcode != aco_opcode::v_fmaak_f32 &&
+ instr->opcode != aco_opcode::v_fmamk_f16 &&
+ instr->opcode != aco_opcode::v_fmaak_f16 &&
+ instr->opcode != aco_opcode::v_readlane_b32 &&
+ instr->opcode != aco_opcode::v_writelane_b32 &&
+ instr->opcode != aco_opcode::v_readfirstlane_b32;
}
bool can_apply_sgprs(aco_ptr<Instruction>& instr)
{
return instr->opcode != aco_opcode::v_readfirstlane_b32 &&
instr->opcode != aco_opcode::v_readlane_b32 &&
- instr->opcode != aco_opcode::v_writelane_b32;
+ instr->opcode != aco_opcode::v_readlane_b32_e64 &&
+ instr->opcode != aco_opcode::v_writelane_b32 &&
+ instr->opcode != aco_opcode::v_writelane_b32_e64;
}
void to_VOP3(opt_ctx& ctx, aco_ptr<Instruction>& instr)
if (instr->isVOP3())
return;
- assert(!instr->operands[0].isLiteral());
aco_ptr<Instruction> tmp = std::move(instr);
Format format = asVOP3(tmp->format);
instr.reset(create_instruction<VOP3A_instruction>(tmp->opcode, format, tmp->operands.size(), tmp->definitions.size()));
}
/* only covers special cases */
-bool can_accept_constant(aco_ptr<Instruction>& instr, unsigned operand)
+bool alu_can_accept_constant(aco_opcode opcode, unsigned operand)
{
- switch (instr->opcode) {
+ switch (opcode) {
case aco_opcode::v_interp_p2_f32:
case aco_opcode::v_mac_f32:
case aco_opcode::v_writelane_b32:
+ case aco_opcode::v_writelane_b32_e64:
case aco_opcode::v_cndmask_b32:
return operand != 2;
case aco_opcode::s_addk_i32:
case aco_opcode::p_extract_vector:
case aco_opcode::p_split_vector:
case aco_opcode::v_readlane_b32:
+ case aco_opcode::v_readlane_b32_e64:
case aco_opcode::v_readfirstlane_b32:
return operand != 0;
default:
- if ((instr->format == Format::MUBUF ||
- instr->format == Format::MIMG) &&
- instr->definitions.size() == 1 &&
- instr->operands.size() == 4) {
- return operand != 3;
- }
return true;
}
}
-bool valu_can_accept_literal(opt_ctx& ctx, aco_ptr<Instruction>& instr, unsigned operand)
+bool valu_can_accept_vgpr(aco_ptr<Instruction>& instr, unsigned operand)
+{
+ if (instr->opcode == aco_opcode::v_readlane_b32 || instr->opcode == aco_opcode::v_readlane_b32_e64 ||
+ instr->opcode == aco_opcode::v_writelane_b32 || instr->opcode == aco_opcode::v_writelane_b32_e64)
+ return operand != 1;
+ return true;
+}
+
+/* check constant bus and literal limitations */
+bool check_vop3_operands(opt_ctx& ctx, unsigned num_operands, Operand *operands)
{
- // TODO: VOP3 can take a literal on GFX10
- return !instr->isSDWA() && !instr->isDPP() && !instr->isVOP3() &&
- operand == 0 && can_accept_constant(instr, operand);
+ int limit = ctx.program->chip_class >= GFX10 ? 2 : 1;
+ Operand literal32(s1);
+ Operand literal64(s2);
+ unsigned num_sgprs = 0;
+ unsigned sgpr[] = {0, 0};
+
+ for (unsigned i = 0; i < num_operands; i++) {
+ Operand op = operands[i];
+
+ if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) {
+ /* two reads of the same SGPR count as 1 to the limit */
+ if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
+ if (num_sgprs < 2)
+ sgpr[num_sgprs++] = op.tempId();
+ limit--;
+ if (limit < 0)
+ return false;
+ }
+ } else if (op.isLiteral()) {
+ if (ctx.program->chip_class < GFX10)
+ return false;
+
+ if (!literal32.isUndefined() && literal32.constantValue() != op.constantValue())
+ return false;
+ if (!literal64.isUndefined() && literal64.constantValue() != op.constantValue())
+ return false;
+
+ /* Any number of 32-bit literals counts as only 1 to the limit. Same
+ * (but separately) for 64-bit literals. */
+ if (op.size() == 1 && literal32.isUndefined()) {
+ limit--;
+ literal32 = op;
+ } else if (op.size() == 2 && literal64.isUndefined()) {
+ limit--;
+ literal64 = op;
+ }
+
+ if (limit < 0)
+ return false;
+ }
+ }
+
+ return true;
}
-bool parse_base_offset(opt_ctx &ctx, Instruction* instr, unsigned op_index, Temp *base, uint32_t *offset)
+bool parse_base_offset(opt_ctx &ctx, Instruction* instr, unsigned op_index, Temp *base, uint32_t *offset, bool prevent_overflow)
{
Operand op = instr->operands[op_index];
switch (add_instr->opcode) {
case aco_opcode::v_add_u32:
case aco_opcode::v_add_co_u32:
+ case aco_opcode::v_add_co_u32_e64:
case aco_opcode::s_add_i32:
case aco_opcode::s_add_u32:
break;
default:
return false;
}
+ if (prevent_overflow && !add_instr->definitions[0].isNUW())
+ return false;
if (add_instr->usesModifiers())
return false;
if (add_instr->operands[i].isConstant()) {
*offset = add_instr->operands[i].constantValue();
} else if (add_instr->operands[i].isTemp() &&
- ctx.info[add_instr->operands[i].tempId()].is_constant_or_literal()) {
+ ctx.info[add_instr->operands[i].tempId()].is_constant_or_literal(32)) {
*offset = ctx.info[add_instr->operands[i].tempId()].val;
} else {
continue;
continue;
uint32_t offset2 = 0;
- if (parse_base_offset(ctx, add_instr, !i, base, &offset2)) {
+ if (parse_base_offset(ctx, add_instr, !i, base, &offset2, prevent_overflow)) {
*offset += offset2;
} else {
*base = add_instr->operands[!i].getTemp();
return false;
}
-void label_instruction(opt_ctx &ctx, aco_ptr<Instruction>& instr)
+unsigned get_operand_size(aco_ptr<Instruction>& instr, unsigned index)
+{
+ if (instr->format == Format::PSEUDO)
+ return instr->operands[index].bytes() * 8u;
+ else if (instr->opcode == aco_opcode::v_mad_u64_u32 || instr->opcode == aco_opcode::v_mad_i64_i32)
+ return index == 2 ? 64 : 32;
+ else if (instr->isVALU() || instr->isSALU())
+ return instr_info.operand_size[(int)instr->opcode];
+ else
+ return 0;
+}
+
+Operand get_constant_op(opt_ctx &ctx, ssa_info info, uint32_t bits)
+{
+ if (bits == 8)
+ return Operand((uint8_t)info.val);
+ if (bits == 16)
+ return Operand((uint16_t)info.val);
+ // TODO: this functions shouldn't be needed if we store Operand instead of value.
+ Operand op(info.val, bits == 64);
+ if (info.is_literal(32) && info.val == 0x3e22f983 && ctx.program->chip_class >= GFX8)
+ op.setFixed(PhysReg{248}); /* 1/2 PI can be an inline constant on GFX8+ */
+ return op;
+}
+
+bool fixed_to_exec(Operand op)
+{
+ return op.isFixed() && op.physReg() == exec;
+}
+
+void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
{
if (instr->isSALU() || instr->isVALU() || instr->format == Format::PSEUDO) {
ASSERTED bool all_const = false;
for (Operand& op : instr->operands)
- all_const = all_const && (!op.isTemp() || ctx.info[op.tempId()].is_constant_or_literal());
+ all_const = all_const && (!op.isTemp() || ctx.info[op.tempId()].is_constant_or_literal(32));
perfwarn(all_const, "All instruction operands are constant", instr.get());
}
/* SALU / PSEUDO: propagate inline constants */
if (instr->isSALU() || instr->format == Format::PSEUDO) {
+ bool is_subdword = false;
+ // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
+ if (instr->format == Format::PSEUDO) {
+ is_subdword = std::any_of(instr->definitions.begin(), instr->definitions.end(),
+ [] (const Definition& def) { return def.regClass().is_subdword();});
+ is_subdword = is_subdword || std::any_of(instr->operands.begin(), instr->operands.end(),
+ [] (const Operand& op) { return op.hasRegClass() && op.regClass().is_subdword();});
+ if (is_subdword && ctx.program->chip_class < GFX9)
+ continue;
+ }
+
if (info.is_temp() && info.temp.type() == RegType::sgpr) {
instr->operands[i].setTemp(info.temp);
info = ctx.info[info.temp.id()];
break;
}
}
- if ((info.is_constant() || (info.is_literal() && instr->format == Format::PSEUDO)) && !instr->operands[i].isFixed() && can_accept_constant(instr, i)) {
- instr->operands[i] = Operand(info.val);
+ unsigned bits = get_operand_size(instr, i);
+ if ((info.is_constant(bits) || (!is_subdword && info.is_literal(bits) && instr->format == Format::PSEUDO)) &&
+ !instr->operands[i].isFixed() && alu_can_accept_constant(instr->opcode, i)) {
+ instr->operands[i] = get_constant_op(ctx, info, bits);
continue;
}
}
/* VALU: propagate neg, abs & inline constants */
else if (instr->isVALU()) {
- if (info.is_temp() && info.temp.type() == RegType::vgpr) {
+ if (info.is_temp() && info.temp.type() == RegType::vgpr && valu_can_accept_vgpr(instr, i)) {
instr->operands[i].setTemp(info.temp);
info = ctx.info[info.temp.id()];
}
- if (info.is_abs() && (can_use_VOP3(instr) || instr->isDPP()) && instr_info.can_use_input_modifiers[(int)instr->opcode]) {
+
+ /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
+ unsigned can_use_mod = instr->opcode != aco_opcode::v_cndmask_b32 || instr->operands[i].getTemp().bytes() == 4;
+ can_use_mod = can_use_mod && instr_info.can_use_input_modifiers[(int)instr->opcode];
+
+ if (info.is_abs() && (can_use_VOP3(ctx, instr) || instr->isDPP()) && can_use_mod) {
if (!instr->isDPP())
to_VOP3(ctx, instr);
instr->operands[i] = Operand(info.temp);
instr->opcode = i ? aco_opcode::v_sub_f32 : aco_opcode::v_subrev_f32;
instr->operands[i].setTemp(info.temp);
continue;
- } else if (info.is_neg() && (can_use_VOP3(instr) || instr->isDPP()) && instr_info.can_use_input_modifiers[(int)instr->opcode]) {
+ } else if (info.is_neg() && instr->opcode == aco_opcode::v_add_f16) {
+ instr->opcode = i ? aco_opcode::v_sub_f16 : aco_opcode::v_subrev_f16;
+ instr->operands[i].setTemp(info.temp);
+ continue;
+ } else if (info.is_neg() && (can_use_VOP3(ctx, instr) || instr->isDPP()) && can_use_mod) {
if (!instr->isDPP())
to_VOP3(ctx, instr);
instr->operands[i].setTemp(info.temp);
static_cast<VOP3A_instruction*>(instr.get())->neg[i] = true;
continue;
}
- if (info.is_constant() && can_accept_constant(instr, i)) {
+ unsigned bits = get_operand_size(instr, i);
+ if (info.is_constant(bits) && alu_can_accept_constant(instr->opcode, i)) {
+ Operand op = get_constant_op(ctx, info, bits);
perfwarn(instr->opcode == aco_opcode::v_cndmask_b32 && i == 2, "v_cndmask_b32 with a constant selector", instr.get());
- if (i == 0) {
- instr->operands[i] = Operand(info.val);
+ if (i == 0 || instr->opcode == aco_opcode::v_readlane_b32 || instr->opcode == aco_opcode::v_writelane_b32) {
+ instr->operands[i] = op;
continue;
} else if (!instr->isVOP3() && can_swap_operands(instr)) {
instr->operands[i] = instr->operands[0];
- instr->operands[0] = Operand(info.val);
+ instr->operands[0] = op;
continue;
- } else if (can_use_VOP3(instr)) {
+ } else if (can_use_VOP3(ctx, instr)) {
to_VOP3(ctx, instr);
- instr->operands[i] = Operand(info.val);
+ instr->operands[i] = op;
continue;
}
}
while (info.is_temp())
info = ctx.info[info.temp.id()];
- if (mubuf->offen && i == 0 && info.is_constant_or_literal() && mubuf->offset + info.val < 4096) {
+ /* According to AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(), vaddr
+ * overflow for scratch accesses works only on GFX9+ and saddr overflow
+ * never works. Since swizzling is the only thing that separates
+ * scratch accesses and other accesses and swizzling changing how
+ * addressing works significantly, this probably applies to swizzled
+ * MUBUF accesses. */
+ bool vaddr_prevent_overflow = mubuf->swizzled && ctx.program->chip_class < GFX9;
+ bool saddr_prevent_overflow = mubuf->swizzled;
+
+ if (mubuf->offen && i == 1 && info.is_constant_or_literal(32) && mubuf->offset + info.val < 4096) {
assert(!mubuf->idxen);
- instr->operands[i] = Operand(v1);
+ instr->operands[1] = Operand(v1);
mubuf->offset += info.val;
mubuf->offen = false;
continue;
- } else if (i == 2 && info.is_constant_or_literal() && mubuf->offset + info.val < 4096) {
+ } else if (i == 2 && info.is_constant_or_literal(32) && mubuf->offset + info.val < 4096) {
instr->operands[2] = Operand((uint32_t) 0);
mubuf->offset += info.val;
continue;
- } else if (mubuf->offen && i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == v1 && mubuf->offset + offset < 4096) {
+ } else if (mubuf->offen && i == 1 && parse_base_offset(ctx, instr.get(), i, &base, &offset, vaddr_prevent_overflow) &&
+ base.regClass() == v1 && mubuf->offset + offset < 4096) {
assert(!mubuf->idxen);
- instr->operands[i].setTemp(base);
+ instr->operands[1].setTemp(base);
mubuf->offset += offset;
continue;
- } else if (i == 2 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == s1 && mubuf->offset + offset < 4096) {
+ } else if (i == 2 && parse_base_offset(ctx, instr.get(), i, &base, &offset, saddr_prevent_overflow) &&
+ base.regClass() == s1 && mubuf->offset + offset < 4096) {
instr->operands[i].setTemp(base);
mubuf->offset += offset;
continue;
DS_instruction *ds = static_cast<DS_instruction *>(instr.get());
Temp base;
uint32_t offset;
- if (i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == instr->operands[i].regClass()) {
+ bool has_usable_ds_offset = ctx.program->chip_class >= GFX7;
+ if (has_usable_ds_offset &&
+ i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset, false) &&
+ base.regClass() == instr->operands[i].regClass() &&
+ instr->opcode != aco_opcode::ds_swizzle_b32) {
if (instr->opcode == aco_opcode::ds_write2_b32 || instr->opcode == aco_opcode::ds_read2_b32 ||
instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) {
- if (offset % 4 == 0 &&
- ds->offset0 + (offset >> 2) <= 255 &&
- ds->offset1 + (offset >> 2) <= 255) {
+ unsigned mask = (instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) ? 0x7 : 0x3;
+ unsigned shifts = (instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) ? 3 : 2;
+
+ if ((offset & mask) == 0 &&
+ ds->offset0 + (offset >> shifts) <= 255 &&
+ ds->offset1 + (offset >> shifts) <= 255) {
instr->operands[i].setTemp(base);
- ds->offset0 += offset >> 2;
- ds->offset1 += offset >> 2;
+ ds->offset0 += offset >> shifts;
+ ds->offset1 += offset >> shifts;
}
} else {
if (ds->offset0 + offset <= 65535) {
SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr.get());
Temp base;
uint32_t offset;
- if (i == 1 && info.is_constant_or_literal() && info.val <= 0xFFFFF) {
+ bool prevent_overflow = smem->operands[0].size() > 2 || smem->prevent_overflow;
+ if (i == 1 && info.is_constant_or_literal(32) &&
+ ((ctx.program->chip_class == GFX6 && info.val <= 0x3FF) ||
+ (ctx.program->chip_class == GFX7 && info.val <= 0xFFFFFFFF) ||
+ (ctx.program->chip_class >= GFX8 && info.val <= 0xFFFFF))) {
instr->operands[i] = Operand(info.val);
continue;
- } else if (i == 1 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->chip_class >= GFX9) {
+ } else if (i == 1 && parse_base_offset(ctx, instr.get(), i, &base, &offset, prevent_overflow) && base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->chip_class >= GFX9) {
bool soe = smem->operands.size() >= (!smem->definitions.empty() ? 3 : 4);
if (soe &&
- (!ctx.info[smem->operands.back().tempId()].is_constant_or_literal() ||
+ (!ctx.info[smem->operands.back().tempId()].is_constant_or_literal(32) ||
ctx.info[smem->operands.back().tempId()].val != 0)) {
continue;
}
new_instr->operands.back() = Operand(base);
if (!smem->definitions.empty())
new_instr->definitions[0] = smem->definitions[0];
- new_instr->can_reorder = smem->can_reorder;
- new_instr->barrier = smem->barrier;
+ new_instr->sync = smem->sync;
+ new_instr->glc = smem->glc;
+ new_instr->dlc = smem->dlc;
+ new_instr->nv = smem->nv;
+ new_instr->disable_wqm = smem->disable_wqm;
instr.reset(new_instr);
smem = static_cast<SMEM_instruction *>(instr.get());
}
continue;
}
}
+
+ else if (instr->format == Format::PSEUDO_BRANCH) {
+ if (ctx.info[instr->operands[0].tempId()].is_scc_invert()) {
+ /* Flip the branch instruction to get rid of the scc_invert instruction */
+ instr->opcode = instr->opcode == aco_opcode::p_cbranch_z ? aco_opcode::p_cbranch_nz : aco_opcode::p_cbranch_z;
+ instr->operands[0].setTemp(ctx.info[instr->operands[0].tempId()].temp);
+ }
+ }
}
/* if this instruction doesn't define anything, return */
if (instr->definitions.empty())
return;
+ if ((uint16_t) instr->format & (uint16_t) Format::VOPC) {
+ ctx.info[instr->definitions[0].tempId()].set_vopc(instr.get());
+ return;
+ }
+
switch (instr->opcode) {
case aco_opcode::p_create_vector: {
+ bool copy_prop = instr->operands.size() == 1 && instr->operands[0].isTemp() &&
+ instr->operands[0].regClass() == instr->definitions[0].regClass();
+ if (copy_prop) {
+ ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
+ break;
+ }
+
unsigned num_ops = instr->operands.size();
for (const Operand& op : instr->operands) {
if (op.isTemp() && ctx.info[op.tempId()].is_vec())
unsigned k = 0;
for (Operand& old_op : old_vec->operands) {
if (old_op.isTemp() && ctx.info[old_op.tempId()].is_vec()) {
- for (unsigned j = 0; j < ctx.info[old_op.tempId()].instr->operands.size(); j++)
- instr->operands[k++] = ctx.info[old_op.tempId()].instr->operands[j];
+ for (unsigned j = 0; j < ctx.info[old_op.tempId()].instr->operands.size(); j++) {
+ Operand op = ctx.info[old_op.tempId()].instr->operands[j];
+ if (op.isTemp() && ctx.info[op.tempId()].is_temp() &&
+ ctx.info[op.tempId()].temp.type() == instr->definitions[0].regClass().type())
+ op.setTemp(ctx.info[op.tempId()].temp);
+ instr->operands[k++] = op;
+ }
} else {
instr->operands[k++] = old_op;
}
}
assert(k == num_ops);
}
- if (instr->operands.size() == 1 && instr->operands[0].isTemp())
- ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
- else if (instr->definitions[0].getTemp().size() == instr->operands.size())
- ctx.info[instr->definitions[0].tempId()].set_vec(instr.get());
+
+ ctx.info[instr->definitions[0].tempId()].set_vec(instr.get());
break;
}
case aco_opcode::p_split_vector: {
- if (!ctx.info[instr->operands[0].tempId()].is_vec())
+ ssa_info& info = ctx.info[instr->operands[0].tempId()];
+
+ if (info.is_constant_or_literal(32)) {
+ uint32_t val = info.val;
+ for (Definition def : instr->definitions) {
+ uint32_t mask = u_bit_consecutive(0, def.bytes() * 8u);
+ ctx.info[def.tempId()].set_constant(ctx.program->chip_class, val & mask);
+ val >>= def.bytes() * 8u;
+ }
+ break;
+ } else if (!info.is_vec()) {
break;
+ }
+
Instruction* vec = ctx.info[instr->operands[0].tempId()].instr;
- assert(instr->definitions.size() == vec->operands.size());
- for (unsigned i = 0; i < instr->definitions.size(); i++) {
- Operand vec_op = vec->operands[i];
+ unsigned split_offset = 0;
+ unsigned vec_offset = 0;
+ unsigned vec_index = 0;
+ for (unsigned i = 0; i < instr->definitions.size(); split_offset += instr->definitions[i++].bytes()) {
+ while (vec_offset < split_offset && vec_index < vec->operands.size())
+ vec_offset += vec->operands[vec_index++].bytes();
+
+ if (vec_offset != split_offset || vec->operands[vec_index].bytes() != instr->definitions[i].bytes())
+ continue;
+
+ Operand vec_op = vec->operands[vec_index];
if (vec_op.isConstant()) {
- if (vec_op.isLiteral())
- ctx.info[instr->definitions[i].tempId()].set_literal(vec_op.constantValue());
- else
- ctx.info[instr->definitions[i].tempId()].set_constant(vec_op.constantValue());
+ ctx.info[instr->definitions[i].tempId()].set_constant(ctx.program->chip_class, vec_op.constantValue64());
+ } else if (vec_op.isUndefined()) {
+ ctx.info[instr->definitions[i].tempId()].set_undefined();
} else {
assert(vec_op.isTemp());
ctx.info[instr->definitions[i].tempId()].set_temp(vec_op.getTemp());
break;
}
case aco_opcode::p_extract_vector: { /* mov */
- if (!ctx.info[instr->operands[0].tempId()].is_vec())
+ ssa_info& info = ctx.info[instr->operands[0].tempId()];
+ const unsigned index = instr->operands[1].constantValue();
+ const unsigned dst_offset = index * instr->definitions[0].bytes();
+
+ if (info.is_constant_or_literal(32)) {
+ uint32_t mask = u_bit_consecutive(0, instr->definitions[0].bytes() * 8u);
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, (info.val >> (dst_offset * 8u)) & mask);
break;
- Instruction* vec = ctx.info[instr->operands[0].tempId()].instr;
- if (vec->definitions[0].getTemp().size() == vec->operands.size() && /* TODO: what about 64bit or other combinations? */
- vec->operands[0].size() == instr->definitions[0].size()) {
-
- /* convert this extract into a mov instruction */
- Operand vec_op = vec->operands[instr->operands[1].constantValue()];
- bool is_vgpr = instr->definitions[0].getTemp().type() == RegType::vgpr;
- aco_opcode opcode = is_vgpr ? aco_opcode::v_mov_b32 : aco_opcode::s_mov_b32;
- Format format = is_vgpr ? Format::VOP1 : Format::SOP1;
- instr->opcode = opcode;
- instr->format = format;
- instr->operands = {instr->operands.begin(), 1 };
- instr->operands[0] = vec_op;
+ } else if (!info.is_vec()) {
+ break;
+ }
- if (vec_op.isConstant()) {
- if (vec_op.isLiteral())
- ctx.info[instr->definitions[0].tempId()].set_literal(vec_op.constantValue());
- else
- ctx.info[instr->definitions[0].tempId()].set_constant(vec_op.constantValue());
+ /* check if we index directly into a vector element */
+ Instruction* vec = info.instr;
+ unsigned offset = 0;
+
+ for (const Operand& op : vec->operands) {
+ if (offset < dst_offset) {
+ offset += op.bytes();
+ continue;
+ } else if (offset != dst_offset || op.bytes() != instr->definitions[0].bytes()) {
+ break;
+ }
+
+ /* convert this extract into a copy instruction */
+ instr->opcode = aco_opcode::p_parallelcopy;
+ instr->operands.pop_back();
+ instr->operands[0] = op;
+
+ if (op.isConstant()) {
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, op.constantValue64());
+ } else if (op.isUndefined()) {
+ ctx.info[instr->definitions[0].tempId()].set_undefined();
} else {
- assert(vec_op.isTemp());
- ctx.info[instr->definitions[0].tempId()].set_temp(vec_op.getTemp());
+ assert(op.isTemp());
+ ctx.info[instr->definitions[0].tempId()].set_temp(op.getTemp());
}
+ break;
}
break;
}
} else if (instr->usesModifiers()) {
// TODO
} else if (instr->operands[0].isConstant()) {
- if (instr->operands[0].isLiteral())
- ctx.info[instr->definitions[0].tempId()].set_literal(instr->operands[0].constantValue());
- else
- ctx.info[instr->definitions[0].tempId()].set_constant(instr->operands[0].constantValue());
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, instr->operands[0].constantValue64());
} else if (instr->operands[0].isTemp()) {
ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
} else {
break;
case aco_opcode::p_is_helper:
if (!ctx.program->needs_wqm)
- ctx.info[instr->definitions[0].tempId()].set_constant(0u);
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, 0u);
break;
case aco_opcode::s_movk_i32: {
uint32_t v = static_cast<SOPK_instruction*>(instr.get())->imm;
v = v & 0x8000 ? (v | 0xffff0000) : v;
- if (v <= 64 || v >= 0xfffffff0)
- ctx.info[instr->definitions[0].tempId()].set_constant(v);
- else
- ctx.info[instr->definitions[0].tempId()].set_literal(v);
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, v);
break;
}
case aco_opcode::v_bfrev_b32:
case aco_opcode::s_brev_b32: {
if (instr->operands[0].isConstant()) {
uint32_t v = util_bitreverse(instr->operands[0].constantValue());
- if (v <= 64 || v >= 0xfffffff0)
- ctx.info[instr->definitions[0].tempId()].set_constant(v);
- else
- ctx.info[instr->definitions[0].tempId()].set_literal(v);
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, v);
}
break;
}
unsigned size = instr->operands[0].constantValue() & 0x1f;
unsigned start = instr->operands[1].constantValue() & 0x1f;
uint32_t v = ((1u << size) - 1u) << start;
- if (v <= 64 || v >= 0xfffffff0)
- ctx.info[instr->definitions[0].tempId()].set_constant(v);
- else
- ctx.info[instr->definitions[0].tempId()].set_literal(v);
+ ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, v);
}
+ break;
}
+ case aco_opcode::v_mul_f16:
case aco_opcode::v_mul_f32: { /* omod */
/* TODO: try to move the negate/abs modifier to the consumer instead */
if (instr->usesModifiers())
break;
+ bool fp16 = instr->opcode == aco_opcode::v_mul_f16;
+
for (unsigned i = 0; i < 2; i++) {
if (instr->operands[!i].isConstant() && instr->operands[i].isTemp()) {
- if (instr->operands[!i].constantValue() == 0x40000000) { /* 2.0 */
- ctx.info[instr->operands[i].tempId()].set_omod2();
- } else if (instr->operands[!i].constantValue() == 0x40800000) { /* 4.0 */
- ctx.info[instr->operands[i].tempId()].set_omod4();
- } else if (instr->operands[!i].constantValue() == 0x3f000000) { /* 0.5 */
- ctx.info[instr->operands[i].tempId()].set_omod5();
- } else if (instr->operands[!i].constantValue() == 0x3f800000) { /* 1.0 */
+ if (instr->operands[!i].constantValue() == (fp16 ? 0x4000 : 0x40000000)) { /* 2.0 */
+ ctx.info[instr->operands[i].tempId()].set_omod2(instr->definitions[0].getTemp());
+ } else if (instr->operands[!i].constantValue() == (fp16 ? 0x4400 : 0x40800000)) { /* 4.0 */
+ ctx.info[instr->operands[i].tempId()].set_omod4(instr->definitions[0].getTemp());
+ } else if (instr->operands[!i].constantValue() == (fp16 ? 0xb800 : 0x3f000000)) { /* 0.5 */
+ ctx.info[instr->operands[i].tempId()].set_omod5(instr->definitions[0].getTemp());
+ } else if (instr->operands[!i].constantValue() == (fp16 ? 0x3c00 : 0x3f800000) &&
+ !(fp16 ? block.fp_mode.must_flush_denorms16_64 : block.fp_mode.must_flush_denorms32)) { /* 1.0 */
ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[i].getTemp());
} else {
continue;
}
break;
}
- case aco_opcode::v_and_b32: /* abs */
- if (instr->operands[0].constantEquals(0x7FFFFFFF) && instr->operands[1].isTemp())
+ case aco_opcode::v_and_b32: { /* abs */
+ if (!instr->usesModifiers() && instr->operands[1].isTemp() &&
+ instr->operands[1].getTemp().type() == RegType::vgpr &&
+ ((instr->definitions[0].bytes() == 4 && instr->operands[0].constantEquals(0x7FFFFFFFu)) ||
+ (instr->definitions[0].bytes() == 2 && instr->operands[0].constantEquals(0x7FFFu))))
ctx.info[instr->definitions[0].tempId()].set_abs(instr->operands[1].getTemp());
else
ctx.info[instr->definitions[0].tempId()].set_bitwise(instr.get());
break;
+ }
case aco_opcode::v_xor_b32: { /* neg */
- if (instr->operands[0].constantEquals(0x80000000u) && instr->operands[1].isTemp()) {
+ if (!instr->usesModifiers() && instr->operands[1].isTemp() &&
+ ((instr->definitions[0].bytes() == 4 && instr->operands[0].constantEquals(0x80000000u)) ||
+ (instr->definitions[0].bytes() == 2 && instr->operands[0].constantEquals(0x8000u)))) {
if (ctx.info[instr->operands[1].tempId()].is_neg()) {
ctx.info[instr->definitions[0].tempId()].set_temp(ctx.info[instr->operands[1].tempId()].temp);
- } else {
+ } else if (instr->operands[1].getTemp().type() == RegType::vgpr) {
if (ctx.info[instr->operands[1].tempId()].is_abs()) { /* neg(abs(x)) */
instr->operands[1].setTemp(ctx.info[instr->operands[1].tempId()].temp);
instr->opcode = aco_opcode::v_or_b32;
}
break;
}
+ case aco_opcode::v_med3_f16:
case aco_opcode::v_med3_f32: { /* clamp */
VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(instr.get());
- if (vop3->abs[0] || vop3->neg[0] || vop3->opsel[0] ||
- vop3->abs[1] || vop3->neg[1] || vop3->opsel[1] ||
- vop3->abs[2] || vop3->neg[2] || vop3->opsel[2] ||
- vop3->omod != 0)
+ if (vop3->abs[0] || vop3->abs[1] || vop3->abs[2] ||
+ vop3->neg[0] || vop3->neg[1] || vop3->neg[2] ||
+ vop3->omod != 0 || vop3->opsel != 0)
break;
unsigned idx = 0;
bool found_zero = false, found_one = false;
+ bool is_fp16 = instr->opcode == aco_opcode::v_med3_f16;
for (unsigned i = 0; i < 3; i++)
{
if (instr->operands[i].constantEquals(0))
found_zero = true;
- else if (instr->operands[i].constantEquals(0x3f800000)) /* 1.0 */
+ else if (instr->operands[i].constantEquals(is_fp16 ? 0x3c00 : 0x3f800000)) /* 1.0 */
found_one = true;
else
idx = i;
}
if (found_zero && found_one && instr->operands[idx].isTemp()) {
- ctx.info[instr->operands[idx].tempId()].set_clamp();
+ ctx.info[instr->operands[idx].tempId()].set_clamp(instr->definitions[0].getTemp());
}
break;
}
case aco_opcode::v_cndmask_b32:
if (instr->operands[0].constantEquals(0) &&
- instr->operands[1].constantEquals(0xFFFFFFFF) &&
- instr->operands[2].isTemp())
+ instr->operands[1].constantEquals(0xFFFFFFFF))
ctx.info[instr->definitions[0].tempId()].set_vcc(instr->operands[2].getTemp());
else if (instr->operands[0].constantEquals(0) &&
- instr->operands[1].constantEquals(0x3f800000u) &&
- instr->operands[2].isTemp())
+ instr->operands[1].constantEquals(0x3f800000u))
ctx.info[instr->definitions[0].tempId()].set_b2f(instr->operands[2].getTemp());
+ else if (instr->operands[0].constantEquals(0) &&
+ instr->operands[1].constantEquals(1))
+ ctx.info[instr->definitions[0].tempId()].set_b2i(instr->operands[2].getTemp());
+
+ ctx.info[instr->operands[2].tempId()].set_vcc_hint();
break;
case aco_opcode::v_cmp_lg_u32:
if (instr->format == Format::VOPC && /* don't optimize VOP3 / SDWA / DPP */
}
case aco_opcode::v_add_u32:
case aco_opcode::v_add_co_u32:
+ case aco_opcode::v_add_co_u32_e64:
case aco_opcode::s_add_i32:
case aco_opcode::s_add_u32:
ctx.info[instr->definitions[0].tempId()].set_add_sub(instr.get());
break;
case aco_opcode::s_not_b32:
case aco_opcode::s_not_b64:
+ if (ctx.info[instr->operands[0].tempId()].is_uniform_bool()) {
+ ctx.info[instr->definitions[0].tempId()].set_uniform_bitwise();
+ ctx.info[instr->definitions[1].tempId()].set_scc_invert(ctx.info[instr->operands[0].tempId()].temp);
+ } else if (ctx.info[instr->operands[0].tempId()].is_uniform_bitwise()) {
+ ctx.info[instr->definitions[0].tempId()].set_uniform_bitwise();
+ ctx.info[instr->definitions[1].tempId()].set_scc_invert(ctx.info[instr->operands[0].tempId()].instr->definitions[1].getTemp());
+ }
+ ctx.info[instr->definitions[0].tempId()].set_bitwise(instr.get());
+ break;
case aco_opcode::s_and_b32:
case aco_opcode::s_and_b64:
+ if (fixed_to_exec(instr->operands[1]) && instr->operands[0].isTemp()) {
+ if (ctx.info[instr->operands[0].tempId()].is_uniform_bool()) {
+ /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
+ ctx.info[instr->definitions[1].tempId()].set_temp(ctx.info[instr->operands[0].tempId()].temp);
+ ctx.info[instr->definitions[0].tempId()].set_uniform_bool(ctx.info[instr->operands[0].tempId()].temp);
+ break;
+ } else if (ctx.info[instr->operands[0].tempId()].is_uniform_bitwise()) {
+ /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
+ ctx.info[instr->definitions[1].tempId()].set_temp(ctx.info[instr->operands[0].tempId()].instr->definitions[1].getTemp());
+ ctx.info[instr->definitions[0].tempId()].set_uniform_bool(ctx.info[instr->operands[0].tempId()].instr->definitions[1].getTemp());
+ break;
+ } else if (ctx.info[instr->operands[0].tempId()].is_vopc()) {
+ Instruction* vopc_instr = ctx.info[instr->operands[0].tempId()].instr;
+ /* Remove superfluous s_and when the VOPC instruction uses the same exec and thus already produces the same result */
+ if (vopc_instr->pass_flags == instr->pass_flags) {
+ assert(instr->pass_flags > 0);
+ ctx.info[instr->definitions[0].tempId()].set_temp(vopc_instr->definitions[0].getTemp());
+ break;
+ }
+ }
+ }
+ /* fallthrough */
case aco_opcode::s_or_b32:
case aco_opcode::s_or_b64:
case aco_opcode::s_xor_b32:
case aco_opcode::s_xor_b64:
+ if (std::all_of(instr->operands.begin(), instr->operands.end(), [&ctx](const Operand& op) {
+ return op.isTemp() && (ctx.info[op.tempId()].is_uniform_bool() || ctx.info[op.tempId()].is_uniform_bitwise());
+ })) {
+ ctx.info[instr->definitions[0].tempId()].set_uniform_bitwise();
+ }
+ /* fallthrough */
case aco_opcode::s_lshl_b32:
case aco_opcode::v_or_b32:
case aco_opcode::v_lshlrev_b32:
case aco_opcode::v_max_i16:
ctx.info[instr->definitions[0].tempId()].set_minmax(instr.get());
break;
- case aco_opcode::v_cmp_lt_f32:
- case aco_opcode::v_cmp_eq_f32:
- case aco_opcode::v_cmp_le_f32:
- case aco_opcode::v_cmp_gt_f32:
- case aco_opcode::v_cmp_lg_f32:
- case aco_opcode::v_cmp_ge_f32:
- case aco_opcode::v_cmp_o_f32:
- case aco_opcode::v_cmp_u_f32:
- case aco_opcode::v_cmp_nge_f32:
- case aco_opcode::v_cmp_nlg_f32:
- case aco_opcode::v_cmp_ngt_f32:
- case aco_opcode::v_cmp_nle_f32:
- case aco_opcode::v_cmp_neq_f32:
- case aco_opcode::v_cmp_nlt_f32:
- ctx.info[instr->definitions[0].tempId()].set_fcmp(instr.get());
+ case aco_opcode::s_cselect_b64:
+ case aco_opcode::s_cselect_b32:
+ if (instr->operands[0].constantEquals((unsigned) -1) &&
+ instr->operands[1].constantEquals(0)) {
+ /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
+ ctx.info[instr->definitions[0].tempId()].set_uniform_bool(instr->operands[2].getTemp());
+ }
+ if (instr->operands[2].isTemp() && ctx.info[instr->operands[2].tempId()].is_scc_invert()) {
+ /* Flip the operands to get rid of the scc_invert instruction */
+ std::swap(instr->operands[0], instr->operands[1]);
+ instr->operands[2].setTemp(ctx.info[instr->operands[2].tempId()].temp);
+ }
+ break;
+ case aco_opcode::p_wqm:
+ if (instr->operands[0].isTemp() &&
+ ctx.info[instr->operands[0].tempId()].is_scc_invert()) {
+ ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
+ }
break;
default:
break;
}
}
-ALWAYS_INLINE bool get_cmp_info(aco_opcode op, aco_opcode *ordered, aco_opcode *unordered, aco_opcode *inverse)
+ALWAYS_INLINE bool get_cmp_info(aco_opcode op, CmpInfo *info)
{
- *ordered = *unordered = op;
+ info->ordered = aco_opcode::num_opcodes;
+ info->unordered = aco_opcode::num_opcodes;
+ info->ordered_swapped = aco_opcode::num_opcodes;
+ info->unordered_swapped = aco_opcode::num_opcodes;
switch (op) {
- #define CMP(ord, unord) \
- case aco_opcode::v_cmp_##ord##_f32:\
- case aco_opcode::v_cmp_n##unord##_f32:\
- *ordered = aco_opcode::v_cmp_##ord##_f32;\
- *unordered = aco_opcode::v_cmp_n##unord##_f32;\
- *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
+ #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
+ case aco_opcode::v_cmp_##ord##_f##sz:\
+ case aco_opcode::v_cmp_n##unord##_f##sz:\
+ info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
+ info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
+ info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
+ info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
+ info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
+ info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
+ info->size = sz;\
return true;
- CMP(lt, /*n*/ge)
- CMP(eq, /*n*/lg)
- CMP(le, /*n*/gt)
- CMP(gt, /*n*/le)
- CMP(lg, /*n*/eq)
- CMP(ge, /*n*/lt)
+ #define CMP(ord, unord, ord_swap, unord_swap) \
+ CMP2(ord, unord, ord_swap, unord_swap, 16)\
+ CMP2(ord, unord, ord_swap, unord_swap, 32)\
+ CMP2(ord, unord, ord_swap, unord_swap, 64)
+ CMP(lt, /*n*/ge, gt, /*n*/le)
+ CMP(eq, /*n*/lg, eq, /*n*/lg)
+ CMP(le, /*n*/gt, ge, /*n*/lt)
+ CMP(gt, /*n*/le, lt, /*n*/le)
+ CMP(lg, /*n*/eq, lg, /*n*/eq)
+ CMP(ge, /*n*/lt, le, /*n*/gt)
#undef CMP
+ #undef CMP2
+ #define ORD_TEST(sz) \
+ case aco_opcode::v_cmp_u_f##sz:\
+ info->f32 = aco_opcode::v_cmp_u_f32;\
+ info->inverse = aco_opcode::v_cmp_o_f##sz;\
+ info->size = sz;\
+ return true;\
+ case aco_opcode::v_cmp_o_f##sz:\
+ info->f32 = aco_opcode::v_cmp_o_f32;\
+ info->inverse = aco_opcode::v_cmp_u_f##sz;\
+ info->size = sz;\
+ return true;
+ ORD_TEST(16)
+ ORD_TEST(32)
+ ORD_TEST(64)
+ #undef ORD_TEST
default:
return false;
}
aco_opcode get_ordered(aco_opcode op)
{
- aco_opcode ordered, unordered, inverse;
- return get_cmp_info(op, &ordered, &unordered, &inverse) ? ordered : aco_opcode::last_opcode;
+ CmpInfo info;
+ return get_cmp_info(op, &info) ? info.ordered : aco_opcode::num_opcodes;
}
aco_opcode get_unordered(aco_opcode op)
{
- aco_opcode ordered, unordered, inverse;
- return get_cmp_info(op, &ordered, &unordered, &inverse) ? unordered : aco_opcode::last_opcode;
+ CmpInfo info;
+ return get_cmp_info(op, &info) ? info.unordered : aco_opcode::num_opcodes;
}
aco_opcode get_inverse(aco_opcode op)
{
- aco_opcode ordered, unordered, inverse;
- return get_cmp_info(op, &ordered, &unordered, &inverse) ? inverse : aco_opcode::last_opcode;
+ CmpInfo info;
+ return get_cmp_info(op, &info) ? info.inverse : aco_opcode::num_opcodes;
+}
+
+aco_opcode get_f32_cmp(aco_opcode op)
+{
+ CmpInfo info;
+ return get_cmp_info(op, &info) ? info.f32 : aco_opcode::num_opcodes;
+}
+
+unsigned get_cmp_bitsize(aco_opcode op)
+{
+ CmpInfo info;
+ return get_cmp_info(op, &info) ? info.size : 0;
}
bool is_cmp(aco_opcode op)
{
- aco_opcode ordered, unordered, inverse;
- return get_cmp_info(op, &ordered, &unordered, &inverse);
+ CmpInfo info;
+ return get_cmp_info(op, &info) && info.ordered != aco_opcode::num_opcodes;
}
unsigned original_temp_id(opt_ctx &ctx, Temp tmp)
* s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
bool combine_ordering_test(opt_ctx &ctx, aco_ptr<Instruction>& instr)
{
- if (instr->opcode != aco_opcode::s_or_b64 && instr->opcode != aco_opcode::s_and_b64)
+ if (instr->definitions[0].regClass() != ctx.program->lane_mask)
return false;
if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
return false;
+ bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32;
+
bool neg[2] = {false, false};
bool abs[2] = {false, false};
- bool opsel[2] = {false, false};
+ uint8_t opsel = 0;
Instruction *op_instr[2];
Temp op[2];
+ unsigned bitsize = 0;
for (unsigned i = 0; i < 2; i++) {
op_instr[i] = follow_operand(ctx, instr->operands[i], true);
if (!op_instr[i])
return false;
- aco_opcode expected_cmp = instr->opcode == aco_opcode::s_or_b64 ?
- aco_opcode::v_cmp_neq_f32 : aco_opcode::v_cmp_eq_f32;
+ aco_opcode expected_cmp = is_or ? aco_opcode::v_cmp_neq_f32 : aco_opcode::v_cmp_eq_f32;
+ unsigned op_bitsize = get_cmp_bitsize(op_instr[i]->opcode);
- if (op_instr[i]->opcode != expected_cmp)
+ if (get_f32_cmp(op_instr[i]->opcode) != expected_cmp)
+ return false;
+ if (bitsize && op_bitsize != bitsize)
return false;
if (!op_instr[i]->operands[0].isTemp() || !op_instr[i]->operands[1].isTemp())
return false;
if (op_instr[i]->isVOP3()) {
VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(op_instr[i]);
- if (vop3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel[0] != vop3->opsel[1])
+ if (vop3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel == 1 || vop3->opsel == 2)
return false;
neg[i] = vop3->neg[0];
abs[i] = vop3->abs[0];
- opsel[i] = vop3->opsel[0];
+ opsel |= (vop3->opsel & 1) << i;
}
Temp op0 = op_instr[i]->operands[0].getTemp();
Temp op1 = op_instr[i]->operands[1].getTemp();
if (original_temp_id(ctx, op0) != original_temp_id(ctx, op1))
return false;
- /* shouldn't happen yet, but best to be safe */
- if (op1.type() != RegType::vgpr)
- return false;
op[i] = op1;
+ bitsize = op_bitsize;
}
+ if (op[1].type() == RegType::sgpr)
+ std::swap(op[0], op[1]);
+ unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr);
+ if (num_sgprs > (ctx.program->chip_class >= GFX10 ? 2 : 1))
+ return false;
+
ctx.uses[op[0].id()]++;
ctx.uses[op[1].id()]++;
decrease_uses(ctx, op_instr[0]);
decrease_uses(ctx, op_instr[1]);
- aco_opcode new_op = instr->opcode == aco_opcode::s_or_b64 ?
- aco_opcode::v_cmp_u_f32 : aco_opcode::v_cmp_o_f32;
+ aco_opcode new_op = aco_opcode::num_opcodes;
+ switch (bitsize) {
+ case 16:
+ new_op = is_or ? aco_opcode::v_cmp_u_f16 : aco_opcode::v_cmp_o_f16;
+ break;
+ case 32:
+ new_op = is_or ? aco_opcode::v_cmp_u_f32 : aco_opcode::v_cmp_o_f32;
+ break;
+ case 64:
+ new_op = is_or ? aco_opcode::v_cmp_u_f64 : aco_opcode::v_cmp_o_f64;
+ break;
+ }
Instruction *new_instr;
- if (neg[0] || neg[1] || abs[0] || abs[1] || opsel[0] || opsel[1]) {
+ if (neg[0] || neg[1] || abs[0] || abs[1] || opsel || num_sgprs > 1) {
VOP3A_instruction *vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1);
for (unsigned i = 0; i < 2; i++) {
vop3->neg[i] = neg[i];
vop3->abs[i] = abs[i];
- vop3->opsel[i] = opsel[i];
}
+ vop3->opsel = opsel;
new_instr = static_cast<Instruction *>(vop3);
} else {
new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1);
new_instr->definitions[0] = instr->definitions[0];
ctx.info[instr->definitions[0].tempId()].label = 0;
- ctx.info[instr->definitions[0].tempId()].set_fcmp(new_instr);
+ ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
instr.reset(new_instr);
* s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
bool combine_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& instr)
{
- if (instr->opcode != aco_opcode::s_or_b64 && instr->opcode != aco_opcode::s_and_b64)
+ if (instr->definitions[0].regClass() != ctx.program->lane_mask)
return false;
if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
return false;
- aco_opcode expected_nan_test = instr->opcode == aco_opcode::s_or_b64 ?
- aco_opcode::v_cmp_u_f32 : aco_opcode::v_cmp_o_f32;
+ bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32;
+ aco_opcode expected_nan_test = is_or ? aco_opcode::v_cmp_u_f32 : aco_opcode::v_cmp_o_f32;
Instruction *nan_test = follow_operand(ctx, instr->operands[0], true);
Instruction *cmp = follow_operand(ctx, instr->operands[1], true);
if (!nan_test || !cmp)
return false;
- if (cmp->opcode == expected_nan_test)
+ if (get_f32_cmp(cmp->opcode) == expected_nan_test)
std::swap(nan_test, cmp);
- else if (nan_test->opcode != expected_nan_test)
+ else if (get_f32_cmp(nan_test->opcode) != expected_nan_test)
return false;
- if (!is_cmp(cmp->opcode))
+ if (!is_cmp(cmp->opcode) || get_cmp_bitsize(cmp->opcode) != get_cmp_bitsize(nan_test->opcode))
return false;
if (!nan_test->operands[0].isTemp() || !nan_test->operands[1].isTemp())
decrease_uses(ctx, nan_test);
decrease_uses(ctx, cmp);
- aco_opcode new_op = instr->opcode == aco_opcode::s_or_b64 ?
- get_unordered(cmp->opcode) : get_ordered(cmp->opcode);
+ aco_opcode new_op = is_or ? get_unordered(cmp->opcode) : get_ordered(cmp->opcode);
Instruction *new_instr;
if (cmp->isVOP3()) {
VOP3A_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1);
VOP3A_instruction *cmp_vop3 = static_cast<VOP3A_instruction*>(cmp);
memcpy(new_vop3->abs, cmp_vop3->abs, sizeof(new_vop3->abs));
- memcpy(new_vop3->opsel, cmp_vop3->opsel, sizeof(new_vop3->opsel));
memcpy(new_vop3->neg, cmp_vop3->neg, sizeof(new_vop3->neg));
new_vop3->clamp = cmp_vop3->clamp;
new_vop3->omod = cmp_vop3->omod;
+ new_vop3->opsel = cmp_vop3->opsel;
new_instr = new_vop3;
} else {
new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1);
new_instr->definitions[0] = instr->definitions[0];
ctx.info[instr->definitions[0].tempId()].label = 0;
- ctx.info[instr->definitions[0].tempId()].set_fcmp(new_instr);
+ ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
instr.reset(new_instr);
* s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
bool combine_constant_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& instr)
{
- if (instr->opcode != aco_opcode::s_or_b64 && instr->opcode != aco_opcode::s_and_b64)
+ if (instr->definitions[0].regClass() != ctx.program->lane_mask)
return false;
if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
return false;
+ bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32;
+
Instruction *nan_test = follow_operand(ctx, instr->operands[0], true);
Instruction *cmp = follow_operand(ctx, instr->operands[1], true);
if (!nan_test || !cmp)
return false;
- aco_opcode expected_nan_test = instr->opcode == aco_opcode::s_or_b64 ?
- aco_opcode::v_cmp_neq_f32 : aco_opcode::v_cmp_eq_f32;
- if (cmp->opcode == expected_nan_test)
+ aco_opcode expected_nan_test = is_or ? aco_opcode::v_cmp_neq_f32 : aco_opcode::v_cmp_eq_f32;
+ if (get_f32_cmp(cmp->opcode) == expected_nan_test)
std::swap(nan_test, cmp);
- else if (nan_test->opcode != expected_nan_test)
+ else if (get_f32_cmp(nan_test->opcode) != expected_nan_test)
return false;
- if (!is_cmp(cmp->opcode))
+ if (!is_cmp(cmp->opcode) || get_cmp_bitsize(cmp->opcode) != get_cmp_bitsize(nan_test->opcode))
return false;
if (!nan_test->operands[0].isTemp() || !nan_test->operands[1].isTemp())
if (prop_nan0 != prop_nan1)
return false;
+ if (nan_test->isVOP3()) {
+ VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(nan_test);
+ if (vop3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel == 1 || vop3->opsel == 2)
+ return false;
+ }
+
int constant_operand = -1;
for (unsigned i = 0; i < 2; i++) {
if (cmp->operands[i].isTemp() && original_temp_id(ctx, cmp->operands[i].getTemp()) == prop_nan0) {
if (cmp->operands[constant_operand].isConstant()) {
constant = cmp->operands[constant_operand].constantValue();
} else if (cmp->operands[constant_operand].isTemp()) {
- unsigned id = cmp->operands[constant_operand].tempId();
- if (!ctx.info[id].is_constant() && !ctx.info[id].is_literal())
+ Temp tmp = cmp->operands[constant_operand].getTemp();
+ unsigned id = original_temp_id(ctx, tmp);
+ if (!ctx.info[id].is_constant_or_literal(32))
return false;
constant = ctx.info[id].val;
} else {
decrease_uses(ctx, nan_test);
decrease_uses(ctx, cmp);
- aco_opcode new_op = instr->opcode == aco_opcode::s_or_b64 ?
- get_unordered(cmp->opcode) : get_ordered(cmp->opcode);
+ aco_opcode new_op = is_or ? get_unordered(cmp->opcode) : get_ordered(cmp->opcode);
Instruction *new_instr;
if (cmp->isVOP3()) {
VOP3A_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1);
VOP3A_instruction *cmp_vop3 = static_cast<VOP3A_instruction*>(cmp);
memcpy(new_vop3->abs, cmp_vop3->abs, sizeof(new_vop3->abs));
- memcpy(new_vop3->opsel, cmp_vop3->opsel, sizeof(new_vop3->opsel));
memcpy(new_vop3->neg, cmp_vop3->neg, sizeof(new_vop3->neg));
new_vop3->clamp = cmp_vop3->clamp;
new_vop3->omod = cmp_vop3->omod;
+ new_vop3->opsel = cmp_vop3->opsel;
new_instr = new_vop3;
} else {
new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1);
new_instr->definitions[0] = instr->definitions[0];
ctx.info[instr->definitions[0].tempId()].label = 0;
- ctx.info[instr->definitions[0].tempId()].set_fcmp(new_instr);
+ ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
instr.reset(new_instr);
return false;
aco_opcode new_opcode = get_inverse(cmp->opcode);
- if (new_opcode == aco_opcode::last_opcode)
+ if (new_opcode == aco_opcode::num_opcodes)
return false;
if (cmp->operands[0].isTemp())
VOP3A_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_opcode, asVOP3(Format::VOPC), 2, 1);
VOP3A_instruction *cmp_vop3 = static_cast<VOP3A_instruction*>(cmp);
memcpy(new_vop3->abs, cmp_vop3->abs, sizeof(new_vop3->abs));
- memcpy(new_vop3->opsel, cmp_vop3->opsel, sizeof(new_vop3->opsel));
memcpy(new_vop3->neg, cmp_vop3->neg, sizeof(new_vop3->neg));
new_vop3->clamp = cmp_vop3->clamp;
new_vop3->omod = cmp_vop3->omod;
+ new_vop3->opsel = cmp_vop3->opsel;
new_instr = new_vop3;
} else {
new_instr = create_instruction<VOPC_instruction>(new_opcode, Format::VOPC, 2, 1);
new_instr->definitions[0] = instr->definitions[0];
ctx.info[instr->definitions[0].tempId()].label = 0;
- ctx.info[instr->definitions[0].tempId()].set_fcmp(new_instr);
+ ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
instr.reset(new_instr);
* op1(0, op2(1, 2)) if swap = true */
bool match_op3_for_vop3(opt_ctx &ctx, aco_opcode op1, aco_opcode op2,
Instruction* op1_instr, bool swap, const char *shuffle_str,
- Operand operands[3], bool neg[3], bool abs[3], bool opsel[3],
- bool *op1_clamp, unsigned *op1_omod,
+ Operand operands[3], bool neg[3], bool abs[3], uint8_t *opsel,
+ bool *op1_clamp, uint8_t *op1_omod,
bool *inbetween_neg, bool *inbetween_abs, bool *inbetween_opsel)
{
/* checks */
Instruction *op2_instr = follow_operand(ctx, op1_instr->operands[swap]);
if (!op2_instr || op2_instr->opcode != op2)
return false;
+ if (fixed_to_exec(op2_instr->operands[0]) || fixed_to_exec(op2_instr->operands[1]))
+ return false;
VOP3A_instruction *op1_vop3 = op1_instr->isVOP3() ? static_cast<VOP3A_instruction *>(op1_instr) : NULL;
VOP3A_instruction *op2_vop3 = op2_instr->isVOP3() ? static_cast<VOP3A_instruction *>(op2_instr) : NULL;
return false;
if (inbetween_opsel)
- *inbetween_opsel = op1_vop3 ? op1_vop3->opsel[swap] : false;
- else if (op1_vop3 && op1_vop3->opsel[swap])
+ *inbetween_opsel = op1_vop3 ? op1_vop3->opsel & (1 << swap) : false;
+ else if (op1_vop3 && op1_vop3->opsel & (1 << swap))
return false;
int shuffle[3];
operands[shuffle[0]] = op1_instr->operands[!swap];
neg[shuffle[0]] = op1_vop3 ? op1_vop3->neg[!swap] : false;
abs[shuffle[0]] = op1_vop3 ? op1_vop3->abs[!swap] : false;
- opsel[shuffle[0]] = op1_vop3 ? op1_vop3->opsel[!swap] : false;
+ if (op1_vop3 && op1_vop3->opsel & (1 << !swap))
+ *opsel |= 1 << shuffle[0];
for (unsigned i = 0; i < 2; i++) {
operands[shuffle[i + 1]] = op2_instr->operands[i];
neg[shuffle[i + 1]] = op2_vop3 ? op2_vop3->neg[i] : false;
abs[shuffle[i + 1]] = op2_vop3 ? op2_vop3->abs[i] : false;
- opsel[shuffle[i + 1]] = op2_vop3 ? op2_vop3->opsel[i] : false;
+ if (op2_vop3 && op2_vop3->opsel & (1 << i))
+ *opsel |= 1 << shuffle[i + 1];
}
/* check operands */
- unsigned sgpr_id = 0;
- for (unsigned i = 0; i < 3; i++) {
- Operand op = operands[i];
- if (op.isLiteral()) {
- return false;
- } else if (op.isTemp() && op.getTemp().type() == RegType::sgpr) {
- if (sgpr_id && sgpr_id != op.tempId())
- return false;
- sgpr_id = op.tempId();
- }
- }
+ if (!check_vop3_operands(ctx, 3, operands))
+ return false;
return true;
}
void create_vop3_for_op3(opt_ctx& ctx, aco_opcode opcode, aco_ptr<Instruction>& instr,
- Operand operands[3], bool neg[3], bool abs[3], bool opsel[3],
+ Operand operands[3], bool neg[3], bool abs[3], uint8_t opsel,
bool clamp, unsigned omod)
{
VOP3A_instruction *new_instr = create_instruction<VOP3A_instruction>(opcode, Format::VOP3A, 3, 1);
memcpy(new_instr->abs, abs, sizeof(bool[3]));
- memcpy(new_instr->opsel, opsel, sizeof(bool[3]));
memcpy(new_instr->neg, neg, sizeof(bool[3]));
new_instr->clamp = clamp;
new_instr->omod = omod;
+ new_instr->opsel = opsel;
new_instr->operands[0] = operands[0];
new_instr->operands[1] = operands[1];
new_instr->operands[2] = operands[2];
bool combine_three_valu_op(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode op2, aco_opcode new_op, const char *shuffle, uint8_t ops)
{
- uint32_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
+ uint64_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
(label_omod_success | label_clamp_success);
for (unsigned swap = 0; swap < 2; swap++) {
continue;
Operand operands[3];
- bool neg[3], abs[3], opsel[3], clamp;
- unsigned omod;
+ bool neg[3], abs[3], clamp;
+ uint8_t opsel = 0, omod = 0;
if (match_op3_for_vop3(ctx, instr->opcode, op2,
instr.get(), swap, shuffle,
- operands, neg, abs, opsel,
+ operands, neg, abs, &opsel,
&clamp, &omod, NULL, NULL, NULL)) {
ctx.uses[instr->operands[swap].tempId()]--;
create_vop3_for_op3(ctx, new_op, instr, operands, neg, abs, opsel, clamp, omod);
return false;
}
+bool combine_minmax(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode opposite, aco_opcode minmax3)
+{
+ if (combine_three_valu_op(ctx, instr, instr->opcode, minmax3, "012", 1 | 2))
+ return true;
+
+ uint64_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
+ (label_omod_success | label_clamp_success);
+
+ /* min(-max(a, b), c) -> min3(-a, -b, c) *
+ * max(-min(a, b), c) -> max3(-a, -b, c) */
+ for (unsigned swap = 0; swap < 2; swap++) {
+ Operand operands[3];
+ bool neg[3], abs[3], clamp;
+ uint8_t opsel = 0, omod = 0;
+ bool inbetween_neg;
+ if (match_op3_for_vop3(ctx, instr->opcode, opposite,
+ instr.get(), swap, "012",
+ operands, neg, abs, &opsel,
+ &clamp, &omod, &inbetween_neg, NULL, NULL) &&
+ inbetween_neg) {
+ ctx.uses[instr->operands[swap].tempId()]--;
+ neg[1] = true;
+ neg[2] = true;
+ create_vop3_for_op3(ctx, minmax3, instr, operands, neg, abs, opsel, clamp, omod);
+ if (omod_clamp & label_omod_success)
+ ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
+ if (omod_clamp & label_clamp_success)
+ ctx.info[instr->definitions[0].tempId()].set_clamp_success(instr.get());
+ return true;
+ }
+ }
+ return false;
+}
+
/* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
* s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
* s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
/* create instruction */
std::swap(instr->definitions[0], op2_instr->definitions[0]);
+ std::swap(instr->definitions[1], op2_instr->definitions[1]);
ctx.uses[instr->operands[0].tempId()]--;
ctx.info[op2_instr->definitions[0].tempId()].label = 0;
* s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
bool combine_salu_n2(opt_ctx& ctx, aco_ptr<Instruction>& instr)
{
- if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
+ if (instr->definitions[0].isTemp() && ctx.info[instr->definitions[0].tempId()].is_uniform_bool())
return false;
for (unsigned i = 0; i < 2; i++) {
Instruction *op2_instr = follow_operand(ctx, instr->operands[i]);
if (!op2_instr || (op2_instr->opcode != aco_opcode::s_not_b32 && op2_instr->opcode != aco_opcode::s_not_b64))
continue;
+ if (ctx.uses[op2_instr->definitions[1].tempId()] || fixed_to_exec(op2_instr->operands[0]))
+ continue;
+
+ if (instr->operands[!i].isLiteral() && op2_instr->operands[0].isLiteral() &&
+ instr->operands[!i].constantValue() != op2_instr->operands[0].constantValue())
+ continue;
ctx.uses[instr->operands[i].tempId()]--;
instr->operands[0] = instr->operands[!i];
/* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
bool combine_salu_lshl_add(opt_ctx& ctx, aco_ptr<Instruction>& instr)
{
- if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
+ if (instr->opcode == aco_opcode::s_add_i32 && ctx.uses[instr->definitions[1].tempId()])
return false;
for (unsigned i = 0; i < 2; i++) {
Instruction *op2_instr = follow_operand(ctx, instr->operands[i]);
- if (!op2_instr || op2_instr->opcode != aco_opcode::s_lshl_b32 || !op2_instr->operands[1].isConstant())
+ if (!op2_instr || op2_instr->opcode != aco_opcode::s_lshl_b32 ||
+ ctx.uses[op2_instr->definitions[1].tempId()])
+ continue;
+ if (!op2_instr->operands[1].isConstant() || fixed_to_exec(op2_instr->operands[0]))
continue;
uint32_t shift = op2_instr->operands[1].constantValue();
if (shift < 1 || shift > 4)
continue;
+ if (instr->operands[!i].isLiteral() && op2_instr->operands[0].isLiteral() &&
+ instr->operands[!i].constantValue() != op2_instr->operands[0].constantValue())
+ continue;
+
ctx.uses[instr->operands[i].tempId()]--;
instr->operands[1] = instr->operands[!i];
instr->operands[0] = op2_instr->operands[0];
return false;
}
+bool combine_add_sub_b2i(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode new_op, uint8_t ops)
+{
+ if (instr->usesModifiers())
+ return false;
+
+ for (unsigned i = 0; i < 2; i++) {
+ if (!((1 << i) & ops))
+ continue;
+ if (instr->operands[i].isTemp() &&
+ ctx.info[instr->operands[i].tempId()].is_b2i() &&
+ ctx.uses[instr->operands[i].tempId()] == 1) {
+
+ aco_ptr<Instruction> new_instr;
+ if (instr->operands[!i].isTemp() && instr->operands[!i].getTemp().type() == RegType::vgpr) {
+ new_instr.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 2));
+ } else if (ctx.program->chip_class >= GFX10 ||
+ (instr->operands[!i].isConstant() && !instr->operands[!i].isLiteral())) {
+ new_instr.reset(create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOP2), 3, 2));
+ } else {
+ return false;
+ }
+ ctx.uses[instr->operands[i].tempId()]--;
+ new_instr->definitions[0] = instr->definitions[0];
+ new_instr->definitions[1] = instr->definitions.size() == 2 ? instr->definitions[1] :
+ Definition(ctx.program->allocateId(), ctx.program->lane_mask);
+ new_instr->definitions[1].setHint(vcc);
+ new_instr->operands[0] = Operand(0u);
+ new_instr->operands[1] = instr->operands[!i];
+ new_instr->operands[2] = Operand(ctx.info[instr->operands[i].tempId()].temp);
+ instr = std::move(new_instr);
+ ctx.info[instr->definitions[0].tempId()].label = 0;
+ return true;
+ }
+ }
+
+ return false;
+}
+
bool get_minmax_info(aco_opcode op, aco_opcode *min, aco_opcode *max, aco_opcode *min3, aco_opcode *max3, aco_opcode *med3, bool *some_gfx9_only)
{
switch (op) {
bool combine_clamp(opt_ctx& ctx, aco_ptr<Instruction>& instr,
aco_opcode min, aco_opcode max, aco_opcode med)
{
+ /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
+ * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
+ * minVal > maxVal, which means we can always select it to a v_med3_f32 */
aco_opcode other_op;
if (instr->opcode == min)
other_op = max;
else
return false;
- uint32_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
+ uint64_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
(label_omod_success | label_clamp_success);
for (unsigned swap = 0; swap < 2; swap++) {
Operand operands[3];
- bool neg[3], abs[3], opsel[3], clamp, inbetween_neg, inbetween_abs;
- unsigned omod;
+ bool neg[3], abs[3], clamp;
+ uint8_t opsel = 0, omod = 0;
if (match_op3_for_vop3(ctx, instr->opcode, other_op, instr.get(), swap,
- "012", operands, neg, abs, opsel,
- &clamp, &omod, &inbetween_neg, &inbetween_abs, NULL)) {
+ "012", operands, neg, abs, &opsel,
+ &clamp, &omod, NULL, NULL, NULL)) {
int const0_idx = -1, const1_idx = -1;
uint32_t const0 = 0, const1 = 0;
for (int i = 0; i < 3; i++) {
uint32_t val;
if (operands[i].isConstant()) {
val = operands[i].constantValue();
- } else if (operands[i].isTemp() && ctx.uses[operands[i].tempId()] == 1 &&
- ctx.info[operands[i].tempId()].is_constant_or_literal()) {
+ } else if (operands[i].isTemp() && ctx.info[operands[i].tempId()].is_constant_or_literal(32)) {
val = ctx.info[operands[i].tempId()].val;
} else {
continue;
if (const0_idx < 0 || const1_idx < 0)
continue;
- if (opsel[const0_idx])
+ if (opsel & (1 << const0_idx))
const0 >>= 16;
- if (opsel[const1_idx])
+ if (opsel & (1 << const1_idx))
const1 >>= 16;
int lower_idx = const0_idx;
return false;
}
- neg[1] ^= inbetween_neg;
- neg[2] ^= inbetween_neg;
- abs[1] |= inbetween_abs;
- abs[2] |= inbetween_abs;
-
ctx.uses[instr->operands[swap].tempId()]--;
create_vop3_for_op3(ctx, med, instr, operands, neg, abs, opsel, clamp, omod);
if (omod_clamp & label_omod_success)
void apply_sgprs(opt_ctx &ctx, aco_ptr<Instruction>& instr)
{
- /* apply sgprs */
- uint32_t sgpr_idx = 0;
- uint32_t sgpr_info_id = 0;
- bool has_sgpr = false;
- uint32_t sgpr_ssa_id = 0;
- /* find 'best' possible sgpr */
- for (unsigned i = 0; i < instr->operands.size(); i++)
- {
- if (instr->operands[i].isLiteral()) {
- has_sgpr = true;
- break;
- }
+ bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
+ instr->opcode == aco_opcode::v_lshrrev_b64 ||
+ instr->opcode == aco_opcode::v_ashrrev_i64;
+
+ /* find candidates and create the set of sgprs already read */
+ unsigned sgpr_ids[2] = {0, 0};
+ uint32_t operand_mask = 0;
+ bool has_literal = false;
+ for (unsigned i = 0; i < instr->operands.size(); i++) {
+ if (instr->operands[i].isLiteral())
+ has_literal = true;
if (!instr->operands[i].isTemp())
continue;
if (instr->operands[i].getTemp().type() == RegType::sgpr) {
- has_sgpr = true;
- sgpr_ssa_id = instr->operands[i].tempId();
- continue;
+ if (instr->operands[i].tempId() != sgpr_ids[0])
+ sgpr_ids[!!sgpr_ids[0]] = instr->operands[i].tempId();
}
ssa_info& info = ctx.info[instr->operands[i].tempId()];
- if (info.is_temp() && info.temp.type() == RegType::sgpr) {
+ if (info.is_temp() && info.temp.type() == RegType::sgpr)
+ operand_mask |= 1u << i;
+ }
+ unsigned max_sgprs = 1;
+ if (ctx.program->chip_class >= GFX10 && !is_shift64)
+ max_sgprs = 2;
+ if (has_literal)
+ max_sgprs--;
+
+ unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1];
+
+ /* keep on applying sgprs until there is nothing left to be done */
+ while (operand_mask) {
+ uint32_t sgpr_idx = 0;
+ uint32_t sgpr_info_id = 0;
+ uint32_t mask = operand_mask;
+ /* choose a sgpr */
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
uint16_t uses = ctx.uses[instr->operands[i].tempId()];
if (sgpr_info_id == 0 || uses < ctx.uses[sgpr_info_id]) {
sgpr_idx = i;
sgpr_info_id = instr->operands[i].tempId();
}
}
- }
- if (!has_sgpr && sgpr_info_id != 0) {
- ssa_info& info = ctx.info[sgpr_info_id];
+ operand_mask &= ~(1u << sgpr_idx);
+
+ /* Applying two sgprs require making it VOP3, so don't do it unless it's
+ * definitively beneficial.
+ * TODO: this is too conservative because later the use count could be reduced to 1 */
+ if (num_sgprs && ctx.uses[sgpr_info_id] > 1 && !instr->isVOP3())
+ break;
+
+ Temp sgpr = ctx.info[sgpr_info_id].temp;
+ bool new_sgpr = sgpr.id() != sgpr_ids[0] && sgpr.id() != sgpr_ids[1];
+ if (new_sgpr && num_sgprs >= max_sgprs)
+ continue;
+
if (sgpr_idx == 0 || instr->isVOP3()) {
- instr->operands[sgpr_idx] = Operand(info.temp);
- ctx.uses[sgpr_info_id]--;
- ctx.uses[info.temp.id()]++;
+ instr->operands[sgpr_idx] = Operand(sgpr);
} else if (can_swap_operands(instr)) {
instr->operands[sgpr_idx] = instr->operands[0];
- instr->operands[0] = Operand(info.temp);
- ctx.uses[sgpr_info_id]--;
- ctx.uses[info.temp.id()]++;
- } else if (can_use_VOP3(instr)) {
+ instr->operands[0] = Operand(sgpr);
+ /* swap bits using a 4-entry LUT */
+ uint32_t swapped = (0x3120 >> (operand_mask & 0x3)) & 0xf;
+ operand_mask = (operand_mask & ~0x3) | swapped;
+ } else if (can_use_VOP3(ctx, instr)) {
to_VOP3(ctx, instr);
- instr->operands[sgpr_idx] = Operand(info.temp);
- ctx.uses[sgpr_info_id]--;
- ctx.uses[info.temp.id()]++;
- }
-
- /* we can have two sgprs on one instruction if it is the same sgpr! */
- } else if (sgpr_info_id != 0 &&
- sgpr_ssa_id == sgpr_info_id &&
- ctx.uses[sgpr_info_id] == 1 &&
- can_use_VOP3(instr)) {
- to_VOP3(ctx, instr);
- instr->operands[sgpr_idx] = Operand(ctx.info[sgpr_info_id].temp);
+ instr->operands[sgpr_idx] = Operand(sgpr);
+ } else {
+ continue;
+ }
+
+ if (new_sgpr)
+ sgpr_ids[num_sgprs++] = sgpr.id();
ctx.uses[sgpr_info_id]--;
- ctx.uses[ctx.info[sgpr_info_id].temp.id()]++;
+ ctx.uses[sgpr.id()]++;
}
}
-bool apply_omod_clamp(opt_ctx &ctx, aco_ptr<Instruction>& instr)
+bool apply_omod_clamp(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
{
/* check if we could apply omod on predecessor */
- if (instr->opcode == aco_opcode::v_mul_f32) {
- if (instr->operands[1].isTemp() && ctx.info[instr->operands[1].tempId()].is_omod_success()) {
-
+ if (instr->opcode == aco_opcode::v_mul_f32 || instr->opcode == aco_opcode::v_mul_f16) {
+ bool op0 = instr->operands[0].isTemp() && ctx.info[instr->operands[0].tempId()].is_omod_success();
+ bool op1 = instr->operands[1].isTemp() && ctx.info[instr->operands[1].tempId()].is_omod_success();
+ if (op0 || op1) {
+ unsigned idx = op0 ? 0 : 1;
/* omod was successfully applied */
/* if the omod instruction is v_mad, we also have to change the original add */
- if (ctx.info[instr->operands[1].tempId()].is_mad()) {
- Instruction* add_instr = ctx.mad_infos[ctx.info[instr->operands[1].tempId()].val].add_instr.get();
+ if (ctx.info[instr->operands[idx].tempId()].is_mad()) {
+ Instruction* add_instr = ctx.mad_infos[ctx.info[instr->operands[idx].tempId()].instr->pass_flags].add_instr.get();
if (ctx.info[instr->definitions[0].tempId()].is_clamp())
static_cast<VOP3A_instruction*>(add_instr)->clamp = true;
add_instr->definitions[0] = instr->definitions[0];
}
- Instruction* omod_instr = ctx.info[instr->operands[1].tempId()].instr;
+ Instruction* omod_instr = ctx.info[instr->operands[idx].tempId()].instr;
/* check if we have an additional clamp modifier */
- if (ctx.info[instr->definitions[0].tempId()].is_clamp() && ctx.uses[instr->definitions[0].tempId()] == 1) {
+ if (ctx.info[instr->definitions[0].tempId()].is_clamp() && ctx.uses[instr->definitions[0].tempId()] == 1 &&
+ ctx.uses[ctx.info[instr->definitions[0].tempId()].temp.id()]) {
static_cast<VOP3A_instruction*>(omod_instr)->clamp = true;
ctx.info[instr->definitions[0].tempId()].set_clamp_success(omod_instr);
}
omod_instr->definitions[0] = instr->definitions[0];
/* change the definition of instr to something unused, e.g. the original omod def */
- instr->definitions[0] = Definition(instr->operands[1].getTemp());
+ instr->definitions[0] = Definition(instr->operands[idx].getTemp());
ctx.uses[instr->definitions[0].tempId()] = 0;
return true;
}
}
/* check if we could apply clamp on predecessor */
- if (instr->opcode == aco_opcode::v_med3_f32) {
+ if (instr->opcode == aco_opcode::v_med3_f32 || instr->opcode == aco_opcode::v_med3_f16) {
+ bool is_fp16 = instr->opcode == aco_opcode::v_med3_f16;
unsigned idx = 0;
bool found_zero = false, found_one = false;
for (unsigned i = 0; i < 3; i++)
{
if (instr->operands[i].constantEquals(0))
found_zero = true;
- else if (instr->operands[i].constantEquals(0x3f800000)) /* 1.0 */
+ else if (instr->operands[i].constantEquals(is_fp16 ? 0x3c00 : 0x3f800000)) /* 1.0 */
found_one = true;
else
idx = i;
/* clamp was successfully applied */
/* if the clamp instruction is v_mad, we also have to change the original add */
if (ctx.info[instr->operands[idx].tempId()].is_mad()) {
- Instruction* add_instr = ctx.mad_infos[ctx.info[instr->operands[idx].tempId()].val].add_instr.get();
+ Instruction* add_instr = ctx.mad_infos[ctx.info[instr->operands[idx].tempId()].instr->pass_flags].add_instr.get();
add_instr->definitions[0] = instr->definitions[0];
}
Instruction* clamp_instr = ctx.info[instr->operands[idx].tempId()].instr;
}
}
+ /* omod has no effect if denormals are enabled */
/* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
if (!instr->definitions.empty() && ctx.uses[instr->definitions[0].tempId()] == 1 &&
- can_use_VOP3(instr) && instr_info.can_use_output_modifiers[(int)instr->opcode]) {
- if(ctx.info[instr->definitions[0].tempId()].is_omod2()) {
+ can_use_VOP3(ctx, instr) && instr_info.can_use_output_modifiers[(int)instr->opcode]) {
+ bool can_use_omod = (instr->definitions[0].bytes() == 4 ? block.fp_mode.denorm32 : block.fp_mode.denorm16_64) == 0;
+ ssa_info& def_info = ctx.info[instr->definitions[0].tempId()];
+ if (can_use_omod && def_info.is_omod2() && ctx.uses[def_info.temp.id()]) {
to_VOP3(ctx, instr);
static_cast<VOP3A_instruction*>(instr.get())->omod = 1;
- ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
- } else if (ctx.info[instr->definitions[0].tempId()].is_omod4()) {
+ def_info.set_omod_success(instr.get());
+ } else if (can_use_omod && def_info.is_omod4() && ctx.uses[def_info.temp.id()]) {
to_VOP3(ctx, instr);
static_cast<VOP3A_instruction*>(instr.get())->omod = 2;
- ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
- } else if (ctx.info[instr->definitions[0].tempId()].is_omod5()) {
+ def_info.set_omod_success(instr.get());
+ } else if (can_use_omod && def_info.is_omod5() && ctx.uses[def_info.temp.id()]) {
to_VOP3(ctx, instr);
static_cast<VOP3A_instruction*>(instr.get())->omod = 3;
- ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
- } else if (ctx.info[instr->definitions[0].tempId()].is_clamp()) {
+ def_info.set_omod_success(instr.get());
+ } else if (def_info.is_clamp() && ctx.uses[def_info.temp.id()]) {
to_VOP3(ctx, instr);
static_cast<VOP3A_instruction*>(instr.get())->clamp = true;
- ctx.info[instr->definitions[0].tempId()].set_clamp_success(instr.get());
+ def_info.set_clamp_success(instr.get());
}
}
// TODO: we could possibly move the whole label_instruction pass to combine_instruction:
// this would mean that we'd have to fix the instruction uses while value propagation
-void combine_instruction(opt_ctx &ctx, aco_ptr<Instruction>& instr)
+void combine_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
{
- if (instr->definitions.empty() || !ctx.uses[instr->definitions[0].tempId()])
+ if (instr->definitions.empty() || is_dead(ctx.uses, instr.get()))
return;
if (instr->isVALU()) {
if (can_apply_sgprs(instr))
apply_sgprs(ctx, instr);
- if (apply_omod_clamp(ctx, instr))
+ if (apply_omod_clamp(ctx, block, instr))
return;
}
+ if (ctx.info[instr->definitions[0].tempId()].is_vcc_hint()) {
+ instr->definitions[0].setHint(vcc);
+ }
+
/* TODO: There are still some peephole optimizations that could be done:
* - abs(a - b) -> s_absdiff_i32
* - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
Definition def = instr->definitions[0];
/* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
bool is_abs = ctx.info[instr->definitions[0].tempId()].is_abs();
- instr.reset(create_instruction<VOP3A_instruction>(aco_opcode::v_mul_f32, asVOP3(Format::VOP2), 2, 1));
+ instr.reset(create_instruction<VOP3A_instruction>(mul_instr->opcode, asVOP3(Format::VOP2), 2, 1));
instr->operands[0] = mul_instr->operands[0];
instr->operands[1] = mul_instr->operands[1];
instr->definitions[0] = def;
ctx.info[instr->definitions[0].tempId()].set_mul(instr.get());
return;
}
+
/* combine mul+add -> mad */
- else if (instr->opcode == aco_opcode::v_add_f32 ||
- instr->opcode == aco_opcode::v_sub_f32 ||
- instr->opcode == aco_opcode::v_subrev_f32) {
+ bool mad32 = instr->opcode == aco_opcode::v_add_f32 ||
+ instr->opcode == aco_opcode::v_sub_f32 ||
+ instr->opcode == aco_opcode::v_subrev_f32;
+ bool mad16 = instr->opcode == aco_opcode::v_add_f16 ||
+ instr->opcode == aco_opcode::v_sub_f16 ||
+ instr->opcode == aco_opcode::v_subrev_f16;
+ if (mad16 || mad32) {
+ bool need_fma = mad32 ? block.fp_mode.denorm32 != 0 :
+ (block.fp_mode.denorm16_64 != 0 || ctx.program->chip_class >= GFX10);
+ if (need_fma && instr->definitions[0].isPrecise())
+ return;
+ if (need_fma && mad32 && !ctx.program->has_fast_fma32)
+ return;
uint32_t uses_src0 = UINT32_MAX;
uint32_t uses_src1 = UINT32_MAX;
Instruction* mul_instr = nullptr;
unsigned add_op_idx;
/* check if any of the operands is a multiplication */
- if (instr->operands[0].isTemp() && ctx.info[instr->operands[0].tempId()].is_mul())
+ ssa_info *op0_info = instr->operands[0].isTemp() ? &ctx.info[instr->operands[0].tempId()] : NULL;
+ ssa_info *op1_info = instr->operands[1].isTemp() ? &ctx.info[instr->operands[1].tempId()] : NULL;
+ if (op0_info && op0_info->is_mul() && (!need_fma || !op0_info->instr->definitions[0].isPrecise()))
uses_src0 = ctx.uses[instr->operands[0].tempId()];
- if (instr->operands[1].isTemp() && ctx.info[instr->operands[1].tempId()].is_mul())
+ if (op1_info && op1_info->is_mul() && (!need_fma || !op1_info->instr->definitions[0].isPrecise()))
uses_src1 = ctx.uses[instr->operands[1].tempId()];
/* find the 'best' mul instruction to combine with the add */
if (uses_src0 < uses_src1) {
- mul_instr = ctx.info[instr->operands[0].tempId()].instr;
+ mul_instr = op0_info->instr;
add_op_idx = 1;
} else if (uses_src1 < uses_src0) {
- mul_instr = ctx.info[instr->operands[1].tempId()].instr;
+ mul_instr = op1_info->instr;
add_op_idx = 0;
} else if (uses_src0 != UINT32_MAX) {
/* tiebreaker: quite random what to pick */
- if (ctx.info[instr->operands[0].tempId()].instr->operands[0].isLiteral()) {
- mul_instr = ctx.info[instr->operands[1].tempId()].instr;
+ if (op0_info->instr->operands[0].isLiteral()) {
+ mul_instr = op1_info->instr;
add_op_idx = 0;
} else {
- mul_instr = ctx.info[instr->operands[0].tempId()].instr;
+ mul_instr = op0_info->instr;
add_op_idx = 1;
}
}
bool abs[3] = {false, false, false};
unsigned omod = 0;
bool clamp = false;
- bool need_vop3 = false;
- int num_sgpr = 0;
op[0] = mul_instr->operands[0];
op[1] = mul_instr->operands[1];
op[2] = instr->operands[add_op_idx];
- for (unsigned i = 0; i < 3; i++)
- {
- if (op[i].isLiteral())
- return;
- if (op[i].isTemp() && op[i].getTemp().type() == RegType::sgpr)
- num_sgpr++;
- if (!(i == 0 || (op[i].isTemp() && op[i].getTemp().type() == RegType::vgpr)))
- need_vop3 = true;
- }
// TODO: would be better to check this before selecting a mul instr?
- if (num_sgpr > 1)
+ if (!check_vop3_operands(ctx, 3, op))
return;
if (mul_instr->isVOP3()) {
neg[1] = vop3->neg[1];
abs[0] = vop3->abs[0];
abs[1] = vop3->abs[1];
- need_vop3 = true;
/* we cannot use these modifiers between mul and add */
if (vop3->clamp || vop3->omod)
return;
}
/* neg of the multiplication result */
neg[1] = neg[1] ^ vop3->neg[1 - add_op_idx];
- need_vop3 = true;
}
- if (instr->opcode == aco_opcode::v_sub_f32) {
+ if (instr->opcode == aco_opcode::v_sub_f32 || instr->opcode == aco_opcode::v_sub_f16)
neg[1 + add_op_idx] = neg[1 + add_op_idx] ^ true;
- need_vop3 = true;
- } else if (instr->opcode == aco_opcode::v_subrev_f32) {
+ else if (instr->opcode == aco_opcode::v_subrev_f32 || instr->opcode == aco_opcode::v_subrev_f16)
neg[2 - add_op_idx] = neg[2 - add_op_idx] ^ true;
- need_vop3 = true;
- }
- aco_ptr<VOP3A_instruction> mad{create_instruction<VOP3A_instruction>(aco_opcode::v_mad_f32, Format::VOP3A, 3, 1)};
+ aco_opcode mad_op = need_fma ? aco_opcode::v_fma_f32 : aco_opcode::v_mad_f32;
+ if (mad16)
+ mad_op = need_fma ? (ctx.program->chip_class == GFX8 ? aco_opcode::v_fma_legacy_f16 : aco_opcode::v_fma_f16) :
+ (ctx.program->chip_class == GFX8 ? aco_opcode::v_mad_legacy_f16 : aco_opcode::v_mad_f16);
+
+ aco_ptr<VOP3A_instruction> mad{create_instruction<VOP3A_instruction>(mad_op, Format::VOP3A, 3, 1)};
for (unsigned i = 0; i < 3; i++)
{
mad->operands[i] = op[i];
mad->definitions[0] = instr->definitions[0];
/* mark this ssa_def to be re-checked for profitability and literals */
- ctx.mad_infos.emplace_back(std::move(instr), mul_instr->definitions[0].tempId(), need_vop3);
+ ctx.mad_infos.emplace_back(std::move(instr), mul_instr->definitions[0].tempId());
ctx.info[mad->definitions[0].tempId()].set_mad(mad.get(), ctx.mad_infos.size() - 1);
instr.reset(mad.release());
return;
}
}
} else if (instr->opcode == aco_opcode::v_or_b32 && ctx.program->chip_class >= GFX9) {
- if (combine_three_valu_op(ctx, instr, aco_opcode::v_or_b32, aco_opcode::v_or3_b32, "012", 1 | 2)) ;
+ if (combine_three_valu_op(ctx, instr, aco_opcode::s_or_b32, aco_opcode::v_or3_b32, "012", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::v_or_b32, aco_opcode::v_or3_b32, "012", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::s_and_b32, aco_opcode::v_and_or_b32, "120", 1 | 2)) ;
else if (combine_three_valu_op(ctx, instr, aco_opcode::v_and_b32, aco_opcode::v_and_or_b32, "120", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::s_lshl_b32, aco_opcode::v_lshl_or_b32, "120", 1 | 2)) ;
else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_or_b32, "210", 1 | 2);
- } else if (instr->opcode == aco_opcode::v_add_u32 && ctx.program->chip_class >= GFX9) {
- if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) ;
- else if (combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add3_u32, "012", 1 | 2)) ;
- else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_add_u32, "210", 1 | 2);
+ } else if (instr->opcode == aco_opcode::v_xor_b32 && ctx.program->chip_class >= GFX10) {
+ if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xor3_b32, "012", 1 | 2)) ;
+ else combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xor3_b32, "012", 1 | 2);
+ } else if (instr->opcode == aco_opcode::v_add_u32) {
+ if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2)) ;
+ else if (ctx.program->chip_class >= GFX9) {
+ if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::s_add_i32, aco_opcode::v_add3_u32, "012", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::s_add_u32, aco_opcode::v_add3_u32, "012", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add3_u32, "012", 1 | 2)) ;
+ else if (combine_three_valu_op(ctx, instr, aco_opcode::s_lshl_b32, aco_opcode::v_lshl_add_u32, "120", 1 | 2)) ;
+ else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_add_u32, "210", 1 | 2);
+ }
+ } else if (instr->opcode == aco_opcode::v_add_co_u32 ||
+ instr->opcode == aco_opcode::v_add_co_u32_e64) {
+ combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2);
+ } else if (instr->opcode == aco_opcode::v_sub_u32 ||
+ instr->opcode == aco_opcode::v_sub_co_u32 ||
+ instr->opcode == aco_opcode::v_sub_co_u32_e64) {
+ combine_add_sub_b2i(ctx, instr, aco_opcode::v_subbrev_co_u32, 2);
+ } else if (instr->opcode == aco_opcode::v_subrev_u32 ||
+ instr->opcode == aco_opcode::v_subrev_co_u32 ||
+ instr->opcode == aco_opcode::v_subrev_co_u32_e64) {
+ combine_add_sub_b2i(ctx, instr, aco_opcode::v_subbrev_co_u32, 1);
} else if (instr->opcode == aco_opcode::v_lshlrev_b32 && ctx.program->chip_class >= GFX9) {
combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add_lshl_u32, "120", 2);
} else if ((instr->opcode == aco_opcode::s_add_u32 || instr->opcode == aco_opcode::s_add_i32) && ctx.program->chip_class >= GFX9) {
} else if (instr->opcode == aco_opcode::s_not_b64) {
if (combine_inverse_comparison(ctx, instr)) ;
else combine_salu_not_bitwise(ctx, instr);
- } else if (instr->opcode == aco_opcode::s_and_b32 || instr->opcode == aco_opcode::s_or_b32) {
- combine_salu_n2(ctx, instr);
- } else if (instr->opcode == aco_opcode::s_and_b64 || instr->opcode == aco_opcode::s_or_b64) {
+ } else if (instr->opcode == aco_opcode::s_and_b32 || instr->opcode == aco_opcode::s_or_b32 ||
+ instr->opcode == aco_opcode::s_and_b64 || instr->opcode == aco_opcode::s_or_b64) {
if (combine_ordering_test(ctx, instr)) ;
else if (combine_comparison_ordering(ctx, instr)) ;
else if (combine_constant_comparison_ordering(ctx, instr)) ;
bool some_gfx9_only;
if (get_minmax_info(instr->opcode, &min, &max, &min3, &max3, &med3, &some_gfx9_only) &&
(!some_gfx9_only || ctx.program->chip_class >= GFX9)) {
- if (combine_three_valu_op(ctx, instr, instr->opcode, instr->opcode == min ? min3 : max3, "012", 1 | 2));
+ if (combine_minmax(ctx, instr, instr->opcode == min ? max : min, instr->opcode == min ? min3 : max3)) ;
else combine_clamp(ctx, instr, min, max, med3);
}
}
}
+bool to_uniform_bool_instr(opt_ctx &ctx, aco_ptr<Instruction> &instr)
+{
+ switch (instr->opcode) {
+ case aco_opcode::s_and_b32:
+ case aco_opcode::s_and_b64:
+ instr->opcode = aco_opcode::s_and_b32;
+ break;
+ case aco_opcode::s_or_b32:
+ case aco_opcode::s_or_b64:
+ instr->opcode = aco_opcode::s_or_b32;
+ break;
+ case aco_opcode::s_xor_b32:
+ case aco_opcode::s_xor_b64:
+ instr->opcode = aco_opcode::s_absdiff_i32;
+ break;
+ default:
+ /* Don't transform other instructions. They are very unlikely to appear here. */
+ return false;
+ }
+
+ for (Operand &op : instr->operands) {
+ ctx.uses[op.tempId()]--;
+
+ if (ctx.info[op.tempId()].is_uniform_bool()) {
+ /* Just use the uniform boolean temp. */
+ op.setTemp(ctx.info[op.tempId()].temp);
+ } else if (ctx.info[op.tempId()].is_uniform_bitwise()) {
+ /* Use the SCC definition of the predecessor instruction.
+ * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
+ * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
+ */
+ Instruction *pred_instr = ctx.info[op.tempId()].instr;
+ assert(pred_instr->definitions.size() >= 2);
+ assert(pred_instr->definitions[1].isFixed() && pred_instr->definitions[1].physReg() == scc);
+ op.setTemp(pred_instr->definitions[1].getTemp());
+ } else {
+ unreachable("Invalid operand on uniform bitwise instruction.");
+ }
+
+ ctx.uses[op.tempId()]++;
+ }
+
+ instr->definitions[0].setTemp(Temp(instr->definitions[0].tempId(), s1));
+ assert(instr->operands[0].regClass() == s1);
+ assert(instr->operands[1].regClass() == s1);
+ return true;
+}
void select_instruction(opt_ctx &ctx, aco_ptr<Instruction>& instr)
{
const uint32_t threshold = 4;
- /* Dead Code Elimination:
- * We remove instructions if they define temporaries which all are unused */
- const bool is_used = instr->definitions.empty() ||
- std::any_of(instr->definitions.begin(), instr->definitions.end(),
- [&ctx](const Definition& def) { return ctx.uses[def.tempId()]; });
- if (!is_used) {
+ if (is_dead(ctx.uses, instr.get())) {
instr.reset();
return;
}
- /* convert split_vector into extract_vector if only one definition is ever used */
+ /* convert split_vector into a copy or extract_vector if only one definition is ever used */
if (instr->opcode == aco_opcode::p_split_vector) {
unsigned num_used = 0;
unsigned idx = 0;
- for (unsigned i = 0; i < instr->definitions.size(); i++) {
+ unsigned split_offset = 0;
+ for (unsigned i = 0, offset = 0; i < instr->definitions.size(); offset += instr->definitions[i++].bytes()) {
if (ctx.uses[instr->definitions[i].tempId()]) {
num_used++;
idx = i;
+ split_offset = offset;
+ }
+ }
+ bool done = false;
+ if (num_used == 1 && ctx.info[instr->operands[0].tempId()].is_vec() &&
+ ctx.uses[instr->operands[0].tempId()] == 1) {
+ Instruction *vec = ctx.info[instr->operands[0].tempId()].instr;
+
+ unsigned off = 0;
+ Operand op;
+ for (Operand& vec_op : vec->operands) {
+ if (off == split_offset) {
+ op = vec_op;
+ break;
+ }
+ off += vec_op.bytes();
+ }
+ if (off != instr->operands[0].bytes() && op.bytes() == instr->definitions[idx].bytes()) {
+ ctx.uses[instr->operands[0].tempId()]--;
+ for (Operand& vec_op : vec->operands) {
+ if (vec_op.isTemp())
+ ctx.uses[vec_op.tempId()]--;
+ }
+ if (op.isTemp())
+ ctx.uses[op.tempId()]++;
+
+ aco_ptr<Pseudo_instruction> extract{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 1, 1)};
+ extract->operands[0] = op;
+ extract->definitions[0] = instr->definitions[idx];
+ instr.reset(extract.release());
+
+ done = true;
}
}
- if (num_used == 1) {
+
+ if (!done && num_used == 1 &&
+ instr->operands[0].bytes() % instr->definitions[idx].bytes() == 0 &&
+ split_offset % instr->definitions[idx].bytes() == 0) {
aco_ptr<Pseudo_instruction> extract{create_instruction<Pseudo_instruction>(aco_opcode::p_extract_vector, Format::PSEUDO, 2, 1)};
extract->operands[0] = instr->operands[0];
- extract->operands[1] = Operand((uint32_t) idx);
+ extract->operands[1] = Operand((uint32_t) split_offset / instr->definitions[idx].bytes());
extract->definitions[0] = instr->definitions[idx];
instr.reset(extract.release());
}
}
- /* re-check mad instructions */
- if (instr->opcode == aco_opcode::v_mad_f32 && ctx.info[instr->definitions[0].tempId()].is_mad()) {
- mad_info* info = &ctx.mad_infos[ctx.info[instr->definitions[0].tempId()].val];
- /* first, check profitability */
- if (ctx.uses[info->mul_temp_id]) {
- ctx.uses[info->mul_temp_id]++;
- instr.swap(info->add_instr);
+ mad_info* mad_info = NULL;
+ if (!instr->definitions.empty() && ctx.info[instr->definitions[0].tempId()].is_mad()) {
+ mad_info = &ctx.mad_infos[ctx.info[instr->definitions[0].tempId()].instr->pass_flags];
+ /* re-check mad instructions */
+ if (ctx.uses[mad_info->mul_temp_id]) {
+ ctx.uses[mad_info->mul_temp_id]++;
+ if (instr->operands[0].isTemp())
+ ctx.uses[instr->operands[0].tempId()]--;
+ if (instr->operands[1].isTemp())
+ ctx.uses[instr->operands[1].tempId()]--;
+ instr.swap(mad_info->add_instr);
+ mad_info = NULL;
+ }
+ /* check literals */
+ else if (!instr->usesModifiers()) {
+ /* FMA can only take literals on GFX10+ */
+ if ((instr->opcode == aco_opcode::v_fma_f32 || instr->opcode == aco_opcode::v_fma_f16) &&
+ ctx.program->chip_class < GFX10)
+ return;
- /* second, check possible literals */
- } else if (!info->needs_vop3) {
+ bool sgpr_used = false;
uint32_t literal_idx = 0;
uint32_t literal_uses = UINT32_MAX;
for (unsigned i = 0; i < instr->operands.size(); i++)
{
+ if (instr->operands[i].isConstant() && i > 0) {
+ literal_uses = UINT32_MAX;
+ break;
+ }
if (!instr->operands[i].isTemp())
continue;
- /* if one of the operands is sgpr, we cannot add a literal somewhere else */
- if (instr->operands[i].getTemp().type() == RegType::sgpr) {
- if (ctx.info[instr->operands[i].tempId()].is_literal()) {
+ unsigned bits = get_operand_size(instr, i);
+ /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
+ if (instr->operands[i].getTemp().type() == RegType::sgpr && (i > 0 || ctx.program->chip_class < GFX10)) {
+ if (!sgpr_used && ctx.info[instr->operands[i].tempId()].is_literal(bits)) {
literal_uses = ctx.uses[instr->operands[i].tempId()];
literal_idx = i;
} else {
literal_uses = UINT32_MAX;
}
- break;
- }
- else if (ctx.info[instr->operands[i].tempId()].is_literal() &&
- ctx.uses[instr->operands[i].tempId()] < literal_uses) {
+ sgpr_used = true;
+ /* don't break because we still need to check constants */
+ } else if (!sgpr_used &&
+ ctx.info[instr->operands[i].tempId()].is_literal(bits) &&
+ ctx.uses[instr->operands[i].tempId()] < literal_uses) {
literal_uses = ctx.uses[instr->operands[i].tempId()];
literal_idx = i;
}
}
- if (literal_uses < threshold) {
+
+ /* Limit the number of literals to apply to not increase the code
+ * size too much, but always apply literals for v_mad->v_madak
+ * because both instructions are 64-bit and this doesn't increase
+ * code size.
+ * TODO: try to apply the literals earlier to lower the number of
+ * uses below threshold
+ */
+ if (literal_uses < threshold || literal_idx == 2) {
ctx.uses[instr->operands[literal_idx].tempId()]--;
- info->check_literal = true;
- info->literal_idx = literal_idx;
+ mad_info->check_literal = true;
+ mad_info->literal_idx = literal_idx;
+ return;
}
}
+ }
+
+ /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
+ if (instr->format == Format::PSEUDO_BRANCH &&
+ instr->operands.size() &&
+ instr->operands[0].isTemp()) {
+ ctx.info[instr->operands[0].tempId()].set_scc_needed();
return;
+ } else if ((instr->opcode == aco_opcode::s_cselect_b64 ||
+ instr->opcode == aco_opcode::s_cselect_b32) &&
+ instr->operands[2].isTemp()) {
+ ctx.info[instr->operands[2].tempId()].set_scc_needed();
}
/* check for literals */
+ if (!instr->isSALU() && !instr->isVALU())
+ return;
+
+ /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
+ if (instr->definitions.size() &&
+ ctx.uses[instr->definitions[0].tempId()] == 0 &&
+ ctx.info[instr->definitions[0].tempId()].is_uniform_bitwise()) {
+ bool transform_done = to_uniform_bool_instr(ctx, instr);
+
+ if (transform_done && !ctx.info[instr->definitions[1].tempId()].is_scc_needed()) {
+ /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
+ uint32_t def0_id = instr->definitions[0].getTemp().id();
+ uint32_t def1_id = instr->definitions[1].getTemp().id();
+ instr->definitions[0].setTemp(Temp(def1_id, s1));
+ instr->definitions[1].setTemp(Temp(def0_id, s1));
+ }
+
+ return;
+ }
+
+ if (instr->isSDWA() || instr->isDPP() || (instr->isVOP3() && ctx.program->chip_class < GFX10))
+ return; /* some encodings can't ever take literals */
+
/* we do not apply the literals yet as we don't know if it is profitable */
- if (instr->isSALU()) {
- uint32_t literal_idx = 0;
- uint32_t literal_uses = UINT32_MAX;
- bool has_literal = false;
- for (unsigned i = 0; i < instr->operands.size(); i++)
- {
- if (instr->operands[i].isLiteral()) {
- has_literal = true;
- break;
- }
- if (!instr->operands[i].isTemp())
- continue;
- if (ctx.info[instr->operands[i].tempId()].is_literal() &&
- ctx.uses[instr->operands[i].tempId()] < literal_uses) {
- literal_uses = ctx.uses[instr->operands[i].tempId()];
- literal_idx = i;
- }
+ Operand current_literal(s1);
+
+ unsigned literal_id = 0;
+ unsigned literal_uses = UINT32_MAX;
+ Operand literal(s1);
+ unsigned num_operands = 1;
+ if (instr->isSALU() || (ctx.program->chip_class >= GFX10 && can_use_VOP3(ctx, instr)))
+ num_operands = instr->operands.size();
+ /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
+ else if (instr->isVALU() && instr->operands.size() >= 3)
+ return;
+
+ unsigned sgpr_ids[2] = {0, 0};
+ bool is_literal_sgpr = false;
+ uint32_t mask = 0;
+
+ /* choose a literal to apply */
+ for (unsigned i = 0; i < num_operands; i++) {
+ Operand op = instr->operands[i];
+ unsigned bits = get_operand_size(instr, i);
+
+ if (instr->isVALU() && op.isTemp() && op.getTemp().type() == RegType::sgpr &&
+ op.tempId() != sgpr_ids[0])
+ sgpr_ids[!!sgpr_ids[0]] = op.tempId();
+
+ if (op.isLiteral()) {
+ current_literal = op;
+ continue;
+ } else if (!op.isTemp() || !ctx.info[op.tempId()].is_literal(bits)) {
+ continue;
}
- if (!has_literal && literal_uses < threshold) {
- ctx.uses[instr->operands[literal_idx].tempId()]--;
- if (ctx.uses[instr->operands[literal_idx].tempId()] == 0)
- instr->operands[literal_idx] = Operand(ctx.info[instr->operands[literal_idx].tempId()].val);
+
+ if (!alu_can_accept_constant(instr->opcode, i))
+ continue;
+
+ if (ctx.uses[op.tempId()] < literal_uses) {
+ is_literal_sgpr = op.getTemp().type() == RegType::sgpr;
+ mask = 0;
+ literal = Operand(ctx.info[op.tempId()].val);
+ literal_uses = ctx.uses[op.tempId()];
+ literal_id = op.tempId();
}
- } else if (instr->isVALU() && valu_can_accept_literal(ctx, instr, 0) &&
- instr->operands[0].isTemp() &&
- ctx.info[instr->operands[0].tempId()].is_literal() &&
- ctx.uses[instr->operands[0].tempId()] < threshold) {
- ctx.uses[instr->operands[0].tempId()]--;
- if (ctx.uses[instr->operands[0].tempId()] == 0)
- instr->operands[0] = Operand(ctx.info[instr->operands[0].tempId()].val);
+
+ mask |= (op.tempId() == literal_id) << i;
}
+
+ /* don't go over the constant bus limit */
+ bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
+ instr->opcode == aco_opcode::v_lshrrev_b64 ||
+ instr->opcode == aco_opcode::v_ashrrev_i64;
+ unsigned const_bus_limit = instr->isVALU() ? 1 : UINT32_MAX;
+ if (ctx.program->chip_class >= GFX10 && !is_shift64)
+ const_bus_limit = 2;
+
+ unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1];
+ if (num_sgprs == const_bus_limit && !is_literal_sgpr)
+ return;
+
+ if (literal_id && literal_uses < threshold &&
+ (current_literal.isUndefined() ||
+ (current_literal.size() == literal.size() &&
+ current_literal.constantValue() == literal.constantValue()))) {
+ /* mark the literal to be applied */
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+ if (instr->operands[i].isTemp() && instr->operands[i].tempId() == literal_id)
+ ctx.uses[instr->operands[i].tempId()]--;
+ }
+ }
}
if (!instr)
return;
- /* apply literals on SALU */
- if (instr->isSALU()) {
- for (Operand& op : instr->operands) {
- if (!op.isTemp())
- continue;
- if (op.isLiteral())
- break;
- if (ctx.info[op.tempId()].is_literal() &&
- ctx.uses[op.tempId()] == 0)
- op = Operand(ctx.info[op.tempId()].val);
- }
- }
-
- /* apply literals on VALU */
- else if (instr->isVALU() && !instr->isVOP3() &&
- instr->operands[0].isTemp() &&
- ctx.info[instr->operands[0].tempId()].is_literal() &&
- ctx.uses[instr->operands[0].tempId()] == 0) {
- instr->operands[0] = Operand(ctx.info[instr->operands[0].tempId()].val);
- }
-
/* apply literals on MAD */
- else if (instr->opcode == aco_opcode::v_mad_f32 && ctx.info[instr->definitions[0].tempId()].is_mad()) {
- mad_info* info = &ctx.mad_infos[ctx.info[instr->definitions[0].tempId()].val];
- aco_ptr<Instruction> new_mad;
- if (info->check_literal && ctx.uses[instr->operands[info->literal_idx].tempId()] == 0) {
+ if (!instr->definitions.empty() && ctx.info[instr->definitions[0].tempId()].is_mad()) {
+ mad_info* info = &ctx.mad_infos[ctx.info[instr->definitions[0].tempId()].instr->pass_flags];
+ if (info->check_literal &&
+ (ctx.uses[instr->operands[info->literal_idx].tempId()] == 0 || info->literal_idx == 2)) {
+ aco_ptr<Instruction> new_mad;
+
+ aco_opcode new_op = info->literal_idx == 2 ? aco_opcode::v_madak_f32 : aco_opcode::v_madmk_f32;
+ if (instr->opcode == aco_opcode::v_fma_f32)
+ new_op = info->literal_idx == 2 ? aco_opcode::v_fmaak_f32 : aco_opcode::v_fmamk_f32;
+ else if (instr->opcode == aco_opcode::v_mad_f16 || instr->opcode == aco_opcode::v_mad_legacy_f16)
+ new_op = info->literal_idx == 2 ? aco_opcode::v_madak_f16 : aco_opcode::v_madmk_f16;
+ else if (instr->opcode == aco_opcode::v_fma_f16)
+ new_op = info->literal_idx == 2 ? aco_opcode::v_fmaak_f16 : aco_opcode::v_fmamk_f16;
+
+ new_mad.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 1));
if (info->literal_idx == 2) { /* add literal -> madak */
- new_mad.reset(create_instruction<VOP2_instruction>(aco_opcode::v_madak_f32, Format::VOP2, 3, 1));
new_mad->operands[0] = instr->operands[0];
new_mad->operands[1] = instr->operands[1];
} else { /* mul literal -> madmk */
- new_mad.reset(create_instruction<VOP2_instruction>(aco_opcode::v_madmk_f32, Format::VOP2, 3, 1));
new_mad->operands[0] = instr->operands[1 - info->literal_idx];
new_mad->operands[1] = instr->operands[2];
}
new_mad->operands[2] = Operand(ctx.info[instr->operands[info->literal_idx].tempId()].val);
new_mad->definitions[0] = instr->definitions[0];
- instr.swap(new_mad);
+ ctx.instructions.emplace_back(std::move(new_mad));
+ return;
+ }
+ }
+
+ /* apply literals on other SALU/VALU */
+ if (instr->isSALU() || instr->isVALU()) {
+ for (unsigned i = 0; i < instr->operands.size(); i++) {
+ Operand op = instr->operands[i];
+ unsigned bits = get_operand_size(instr, i);
+ if (op.isTemp() && ctx.info[op.tempId()].is_literal(bits) && ctx.uses[op.tempId()] == 0) {
+ Operand literal(ctx.info[op.tempId()].val);
+ if (instr->isVALU() && i > 0)
+ to_VOP3(ctx, instr);
+ instr->operands[i] = literal;
+ }
}
}
/* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
for (Block& block : program->blocks) {
for (aco_ptr<Instruction>& instr : block.instructions)
- label_instruction(ctx, instr);
+ label_instruction(ctx, block, instr);
}
- ctx.uses = std::move(dead_code_analysis(program));
+ ctx.uses = dead_code_analysis(program);
/* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
for (Block& block : program->blocks) {
for (aco_ptr<Instruction>& instr : block.instructions)
- combine_instruction(ctx, instr);
+ combine_instruction(ctx, block, instr);
}
/* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
projects / mesa.git / blobdiff