ac/llvm: fix unaligned VS input loads on gfx10.3

[mesa.git] / src / amd / llvm / ac_llvm_build.c

diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c
index 6d5d1f7bab27d0ba9fc54830ed4c1b8dd8d24aa6..de9091693c1916fd377e30e777b1ef5cce6422f8 100644 (file)
--- a/src/amd/llvm/ac_llvm_build.c
+++ b/src/amd/llvm/ac_llvm_build.c
@@ -1656,7 +1656,7 @@ ac_build_opencoded_load_format(struct ac_llvm_context *ctx,
        }
 
        int log_recombine = 0;
-       if ((ctx->chip_class == GFX6 || ctx->chip_class == GFX10) && !known_aligned) {
+       if ((ctx->chip_class == GFX6 || ctx->chip_class >= GFX10) && !known_aligned) {
                /* Avoid alignment restrictions by loading one byte at a time. */
                load_num_channels <<= load_log_size;
                log_recombine = load_log_size;
@@ -2727,54 +2727,6 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags)
                           ctx->voidt, args, 1, 0);
 }
 
-LLVMValueRef ac_build_fmed3(struct ac_llvm_context *ctx, LLVMValueRef src0,
-                           LLVMValueRef src1, LLVMValueRef src2,
-                           unsigned bitsize)
-{
-       LLVMValueRef result;
-
-       if (bitsize == 64 || (bitsize == 16 && ctx->chip_class <= GFX8)) {
-               /* Lower 64-bit fmed because LLVM doesn't expose an intrinsic,
-                * or lower 16-bit fmed because it's only supported on GFX9+.
-                */
-               LLVMValueRef min1, min2, max1;
-
-               min1 = ac_build_fmin(ctx, src0, src1);
-               max1 = ac_build_fmax(ctx, src0, src1);
-               min2 = ac_build_fmin(ctx, max1, src2);
-
-               result = ac_build_fmax(ctx, min2, min1);
-       } else {
-               LLVMTypeRef type;
-               char *intr;
-
-               if (bitsize == 16) {
-                       intr = "llvm.amdgcn.fmed3.f16";
-                       type = ctx->f16;
-               } else {
-                       assert(bitsize == 32);
-                       intr = "llvm.amdgcn.fmed3.f32";
-                       type = ctx->f32;
-               }
-
-               LLVMValueRef params[] = {
-                       src0,
-                       src1,
-                       src2,
-               };
-
-               result = ac_build_intrinsic(ctx, intr, type, params, 3,
-                                           AC_FUNC_ATTR_READNONE);
-       }
-
-       if (ctx->chip_class < GFX9 && bitsize == 32) {
-               /* Only pre-GFX9 chips do not flush denorms. */
-               result = ac_build_canonicalize(ctx, result, bitsize);
-       }
-
-       return result;
-}
-
 LLVMValueRef ac_build_fract(struct ac_llvm_context *ctx, LLVMValueRef src0,
                            unsigned bitsize)
 {
@@ -4988,6 +4940,7 @@ ac_build_main(const struct ac_shader_args *args,
                if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
                        ac_add_function_attr(ctx->context, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
                        ac_add_attr_dereferenceable(P, UINT64_MAX);
+                       ac_add_attr_alignment(P, 32);
                }
        }