radv: enable lowering of GS intrinsics for the LLVM backend

[mesa.git] / src / amd / llvm / ac_nir_to_llvm.c

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 84067667ef4cbbce0be7461b78b261ae372f6dd4..627f5d2d931212ccff4dfc57db393c0348acc49d 100644 (file)
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -1741,12 +1741,13 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
                        num_bytes = 2;
                }
 
-               /* Due to alignment issues, split stores of 8-bit vectors. */
-               if (ctx->ac.chip_class == GFX6 &&
-                    elem_size_bytes == 1 && count > 1) {
+               /* Due to alignment issues, split stores of 8-bit/16-bit
+                * vectors.
+                */
+               if (ctx->ac.chip_class == GFX6 && count > 1 && elem_size_bytes < 4) {
                        writemask |= ((1u << (count - 1)) - 1u) << (start + 1);
                        count = 1;
-                       num_bytes = 1;
+                       num_bytes = elem_size_bytes;
                }
 
                data = extract_vector_range(&ctx->ac, base_data, start, count);
@@ -2342,8 +2343,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
                unsigned natural_stride = type_scalar_size_bytes(deref->type);
                unsigned stride = explicit_stride ? explicit_stride : natural_stride;
                int elem_size_bytes = ac_get_elem_bits(&ctx->ac, result_type) / 8;
-               bool split_loads = ctx->ac.chip_class == GFX6 &&
-                                  elem_size_bytes == 1;
+               bool split_loads = ctx->ac.chip_class == GFX6 && elem_size_bytes < 4;
 
                if (stride != natural_stride || split_loads) {
                        if (LLVMGetTypeKind(result_type) == LLVMVectorTypeKind)
@@ -2505,8 +2505,7 @@ visit_store_var(struct ac_nir_context *ctx,
                unsigned natural_stride = type_scalar_size_bytes(deref->type);
                unsigned stride = explicit_stride ? explicit_stride : natural_stride;
                int elem_size_bytes = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(val)) / 8;
-               bool split_stores = ctx->ac.chip_class == GFX6 &&
-                                   elem_size_bytes == 1;
+               bool split_stores = ctx->ac.chip_class == GFX6 && elem_size_bytes < 4;
 
                LLVMTypeRef ptr_type =  LLVMPointerType(LLVMTypeOf(val),
                                                        LLVMGetPointerAddressSpace(LLVMTypeOf(address)));
@@ -3939,7 +3938,16 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
        case nir_intrinsic_emit_vertex:
                ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
                break;
+       case nir_intrinsic_emit_vertex_with_counter: {
+               unsigned stream = nir_intrinsic_stream_id(instr);
+               LLVMValueRef next_vertex = get_src(ctx, instr->src[0]);
+               ctx->abi->emit_vertex_with_counter(ctx->abi, stream,
+                                                  next_vertex,
+                                                  ctx->abi->outputs);
+               break;
+       }
        case nir_intrinsic_end_primitive:
+       case nir_intrinsic_end_primitive_with_counter:
                ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
                break;
        case nir_intrinsic_load_tess_coord: