radeonsi/gfx10: set more registers and fields

[mesa.git] / src / amd / registers / gfx10.json

diff --git a/src/amd/registers/gfx10.json b/src/amd/registers/gfx10.json
index 522af60a72a7fadaf251a27fc254e7d6ec7fb052..ea00d0c7fdc06337a12ecf3a8f70b18f7cc41f79 100644 (file)
--- a/src/amd/registers/gfx10.json
+++ b/src/amd/registers/gfx10.json
@@ -10192,6 +10192,12 @@
    "name": "GE_USER_VGPR3",
    "type_ref": "COMPUTE_PGM_LO"
   },
+  {
+   "chips": ["gfx10"],
+   "map": {"at": 199048, "to": "mm"},
+   "name": "GE_USER_VGPR_EN",
+   "type_ref": "GE_USER_VGPR_EN"
+  },
   {
    "chips": ["gfx10"],
    "map": {"at": 165840, "to": "mm"},
@@ -18944,10 +18950,14 @@
     {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
     {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
     {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
-    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"},
-    {"bits": [21, 21], "name": "EN_USER_VGPR1"},
-    {"bits": [22, 22], "name": "EN_USER_VGPR2"},
-    {"bits": [23, 23], "name": "EN_USER_VGPR3"}
+    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
+   ]
+  },
+  "GE_USER_VGPR_EN": {
+   "fields": [
+    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
+    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
+    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
    ]
   },
   "GE_DMA_FIRST_INDEX": {