radv: Update CTS version.

[mesa.git] / src / amd / vulkan / radv_cs.h

diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index eb1aedb032761983737dde1df98be07372e14cfb..2bef75c80ad86cc730ffc5befa6f007af69dccef 100644 (file)
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -42,7 +42,7 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
 
 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
-        assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONFIG_REG_END);
+        assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END);
         assert(cs->cdw + 2 + num <= cs->max_dw);
         assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
@@ -82,6 +82,18 @@ static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
        radeon_emit(cs, value);
 }
 
+static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs,
+                                             unsigned reg, unsigned value,
+                                             unsigned mask)
+{
+       assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
+       assert(cs->cdw + 4 <= cs->max_dw);
+       radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
+       radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
+       radeon_emit(cs, mask);
+       radeon_emit(cs, value);
+}
+
 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
@@ -97,6 +109,24 @@ static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, uns
        radeon_emit(cs, value);
 }
 
+static inline void radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice,
+                                        struct radeon_cmdbuf *cs,
+                                        unsigned reg, unsigned idx,
+                                        unsigned value)
+{
+       assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
+       assert(cs->cdw + 3 <= cs->max_dw);
+       assert(idx);
+
+       unsigned opcode = PKT3_SET_SH_REG_INDEX;
+       if (pdevice->rad_info.chip_class < GFX10)
+               opcode = PKT3_SET_SH_REG;
+
+       radeon_emit(cs, PKT3(opcode, 1, 0));
+       radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
+       radeon_emit(cs, value);
+}
+
 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
@@ -131,4 +161,20 @@ static inline void radeon_set_uconfig_reg_idx(const struct radv_physical_device
        radeon_emit(cs, value);
 }
 
+static inline void radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs,
+                                                   unsigned reg,
+                                                   unsigned value)
+{
+       assert(reg < CIK_UCONFIG_REG_OFFSET);
+       assert(cs->cdw + 6 <= cs->max_dw);
+
+       radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+       radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
+                       COPY_DATA_DST_SEL(COPY_DATA_PERF));
+       radeon_emit(cs, value);
+       radeon_emit(cs, 0); /* unused */
+       radeon_emit(cs, reg >> 2);
+       radeon_emit(cs, 0); /* unused */
+}
+
 #endif /* RADV_CS_H */