#include "radv_shader.h"
#define TRACE_BO_SIZE 4096
+#define TMA_BO_SIZE 4096
#define COLOR_RESET "\033[0m"
#define COLOR_RED "\033[31m"
device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
RADEON_DOMAIN_VRAM,
RADEON_FLAG_CPU_ACCESS|
- RADEON_FLAG_NO_INTERPROCESS_SHARING,
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ RADEON_FLAG_ZERO_VRAM,
RADV_BO_PRIORITY_UPLOAD_BUFFER);
if (!device->trace_bo)
return false;
if (!device->trace_id_ptr)
return false;
- memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
-
ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
&device->dmesg_timestamp, NULL);
fprintf(f, "\n");
}
-static const char *
-radv_get_descriptor_name(enum VkDescriptorType type)
-{
- switch (type) {
- case VK_DESCRIPTOR_TYPE_SAMPLER:
- return "SAMPLER";
- case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
- return "COMBINED_IMAGE_SAMPLER";
- case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
- return "SAMPLED_IMAGE";
- case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
- return "STORAGE_IMAGE";
- case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
- return "UNIFORM_TEXEL_BUFFER";
- case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
- return "STORAGE_TEXEL_BUFFER";
- case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
- return "UNIFORM_BUFFER";
- case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
- return "STORAGE_BUFFER";
- case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
- return "UNIFORM_BUFFER_DYNAMIC";
- case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
- return "STORAGE_BUFFER_DYNAMIC";
- case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
- return "INPUT_ATTACHMENT";
- default:
- return "UNKNOWN";
- }
-}
-
static void
radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
FILE *f)
}
static void
-radv_dump_descriptor_set(enum chip_class chip_class,
+radv_dump_descriptor_set(struct radv_device *device,
struct radv_descriptor_set *set, unsigned id, FILE *f)
{
+ enum chip_class chip_class = device->physical_device->rad_info.chip_class;
const struct radv_descriptor_set_layout *layout;
int i;
return;
layout = set->layout;
- fprintf(f, "** descriptor set (%d) **\n", id);
- fprintf(f, "va: 0x%"PRIx64"\n", set->va);
- fprintf(f, "size: %d\n", set->size);
- fprintf(f, "mapped_ptr:\n");
-
- for (i = 0; i < set->size / 4; i++) {
- fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]);
- }
- fprintf(f, "\n");
-
- fprintf(f, "\t*** layout ***\n");
- fprintf(f, "\tbinding_count: %d\n", layout->binding_count);
- fprintf(f, "\tsize: %d\n", layout->size);
- fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
- fprintf(f, "\tdynamic_shader_stages: %x\n",
- layout->dynamic_shader_stages);
- fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
- fprintf(f, "\tdynamic_offset_count: %d\n",
- layout->dynamic_offset_count);
- fprintf(f, "\n");
-
for (i = 0; i < set->layout->binding_count; i++) {
uint32_t *desc =
set->mapped_ptr + layout->binding[i].offset / 4;
- fprintf(f, "\t\t**** binding layout (%d) ****\n", i);
- fprintf(f, "\t\ttype: %s\n",
- radv_get_descriptor_name(layout->binding[i].type));
- fprintf(f, "\t\tarray_size: %d\n",
- layout->binding[i].array_size);
- fprintf(f, "\t\toffset: %d\n",
- layout->binding[i].offset);
- fprintf(f, "\t\tbuffer_offset: %d\n",
- layout->binding[i].buffer_offset);
- fprintf(f, "\t\tdynamic_offset_offset: %d\n",
- layout->binding[i].dynamic_offset_offset);
- fprintf(f, "\t\tdynamic_offset_count: %d\n",
- layout->binding[i].dynamic_offset_count);
- fprintf(f, "\t\tsize: %d\n",
- layout->binding[i].size);
- fprintf(f, "\t\timmutable_samplers_offset: %d\n",
- layout->binding[i].immutable_samplers_offset);
- fprintf(f, "\t\timmutable_samplers_equal: %d\n",
- layout->binding[i].immutable_samplers_equal);
- fprintf(f, "\n");
-
switch (layout->binding[i].type) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
}
static void
-radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
+radv_dump_descriptors(struct radv_device *device, FILE *f)
{
- struct radv_device *device = pipeline->device;
- enum chip_class chip_class = device->physical_device->rad_info.chip_class;
uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
int i;
- fprintf(f, "List of descriptors:\n");
+ fprintf(f, "Descriptors:\n");
for (i = 0; i < MAX_SETS; i++) {
struct radv_descriptor_set *set =
- (struct radv_descriptor_set *)ptr[i + 3];
+ *(struct radv_descriptor_set **)(ptr + i + 3);
- radv_dump_descriptor_set(chip_class, set, i, f);
+ radv_dump_descriptor_set(device, set, i, f);
}
}
struct radv_shader_inst *inst = &instructions[*num];
unsigned len = next - disasm;
+ if (!memchr(disasm, ';', len)) {
+ /* Ignore everything that is not an instruction. */
+ disasm = next + 1;
+ continue;
+ }
+
assert(len < ARRAY_SIZE(inst->text));
memcpy(inst->text, disasm, len);
inst->text[len] = 0;
fprintf(f, "NIR:\n%s\n", shader->nir_string);
}
- fprintf(f, "LLVM IR:\n%s\n", shader->ir_string);
+ fprintf(f, "%s IR:\n%s\n",
+ pipeline->device->physical_device->use_llvm ? "LLVM" : "ACO",
+ shader->ir_string);
fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
radv_shader_dump_stats(pipeline->device, shader, stage, f);
{
radv_dump_shaders(pipeline, active_stages, f);
radv_dump_annotated_shaders(pipeline, active_stages, f);
- radv_dump_descriptors(pipeline, f);
}
static void
-radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
+radv_dump_graphics_state(struct radv_device *device,
+ struct radv_pipeline *graphics_pipeline,
struct radv_pipeline *compute_pipeline, FILE *f)
{
VkShaderStageFlagBits active_stages;
active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
radv_dump_pipeline_state(compute_pipeline, active_stages, f);
}
+
+ radv_dump_descriptors(device, f);
}
static void
-radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
+radv_dump_compute_state(struct radv_device *device,
+ struct radv_pipeline *compute_pipeline, FILE *f)
{
VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
return;
radv_dump_pipeline_state(compute_pipeline, active_stages, f);
+ radv_dump_descriptors(device, f);
}
static struct radv_pipeline *
{
uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
- return (struct radv_pipeline *)ptr[1];
+ return *(struct radv_pipeline **)(ptr + 1);
}
static struct radv_pipeline *
{
uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
- return (struct radv_pipeline *)ptr[2];
+ return *(struct radv_pipeline **)(ptr + 2);
}
static void
snprintf(kernel_version, sizeof(kernel_version),
" / %s", uname_data.release);
- fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
- MESA_LLVM_VERSION_STRING ")\n\n",
+ fprintf(f, "Device name: %s (%s / DRM %i.%i.%i%s)\n\n",
chip_name, device->physical_device->name,
info->drm_major, info->drm_minor, info->drm_patchlevel,
kernel_version);
graphics_pipeline = radv_get_saved_graphics_pipeline(device);
compute_pipeline = radv_get_saved_compute_pipeline(device);
+ radv_dump_trace(queue->device, cs);
+
fprintf(stderr, "GPU hang report:\n\n");
radv_dump_device_name(device, stderr);
switch (ring) {
case RING_GFX:
- radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
+ fprintf(stderr, "RING_GFX:\n");
+ radv_dump_graphics_state(queue->device,
+ graphics_pipeline, compute_pipeline,
stderr);
break;
case RING_COMPUTE:
- radv_dump_compute_state(compute_pipeline, stderr);
+ fprintf(stderr, "RING_COMPUTE:\n");
+ radv_dump_compute_state(queue->device,
+ compute_pipeline, stderr);
break;
default:
assert(0);
break;
}
- radv_dump_trace(queue->device, cs);
abort();
}
void
-radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp)
+radv_print_spirv(const char *data, uint32_t size, FILE *fp)
{
char path[] = "/tmp/fileXXXXXX";
char line[2048], command[128];
close(fd);
unlink(path);
}
+
+bool
+radv_trap_handler_init(struct radv_device *device)
+{
+ struct radeon_winsys *ws = device->ws;
+
+ /* Create the trap handler shader and upload it like other shaders. */
+ device->trap_handler_shader = radv_create_trap_handler_shader(device);
+ if (!device->trap_handler_shader) {
+ fprintf(stderr, "radv: failed to create the trap handler shader.\n");
+ return false;
+ }
+
+ device->tma_bo = ws->buffer_create(ws, TMA_BO_SIZE, 8,
+ RADEON_DOMAIN_VRAM,
+ RADEON_FLAG_CPU_ACCESS |
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ RADEON_FLAG_ZERO_VRAM,
+ RADV_BO_PRIORITY_SCRATCH);
+ if (!device->tma_bo)
+ return false;
+
+ device->tma_ptr = ws->buffer_map(device->tma_bo);
+ if (!device->tma_ptr)
+ return false;
+
+ /* Upload a buffer descriptor to store various info from the trap. */
+ uint64_t tma_va = radv_buffer_get_va(device->tma_bo) + 16;
+ uint32_t desc[4];
+
+ desc[0] = tma_va;
+ desc[1] = S_008F04_BASE_ADDRESS_HI(tma_va >> 32);
+ desc[2] = TMA_BO_SIZE;
+ desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+
+ memcpy(device->tma_ptr, desc, sizeof(desc));
+
+ return true;
+}
+
+void
+radv_trap_handler_finish(struct radv_device *device)
+{
+ struct radeon_winsys *ws = device->ws;
+
+ if (unlikely(device->trap_handler_shader))
+ radv_shader_variant_destroy(device, device->trap_handler_shader);
+
+ if (unlikely(device->tma_bo))
+ ws->buffer_destroy(device->tma_bo);
+}
projects / mesa.git / blobdiff