radv: add initial trap handler support with RADV_TRAP_HANDLER=1

[mesa.git] / src / amd / vulkan / radv_debug.c

diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 77a136f94a12d5a8312697c08b280c7d0d972395..6ce76b77eaaa133c9cb410524032951b795b2f2d 100644 (file)
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -36,6 +36,7 @@
 #include "radv_shader.h"
 
 #define TRACE_BO_SIZE 4096
+#define TMA_BO_SIZE 4096
 
 #define COLOR_RESET    "\033[0m"
 #define COLOR_RED      "\033[31m"
@@ -273,6 +274,12 @@ static void si_add_split_disasm(const char *disasm,
                struct radv_shader_inst *inst = &instructions[*num];
                unsigned len = next - disasm;
 
+               if (!memchr(disasm, ';', len)) {
+                       /* Ignore everything that is not an instruction. */
+                       disasm = next + 1;
+                       continue;
+               }
+
                assert(len < ARRAY_SIZE(inst->text));
                memcpy(inst->text, disasm, len);
                inst->text[len] = 0;
@@ -433,7 +440,7 @@ radv_dump_shader(struct radv_pipeline *pipeline,
        }
 
        fprintf(f, "%s IR:\n%s\n",
-               pipeline->device->physical_device->use_aco ? "ACO" : "LLVM",
+               pipeline->device->physical_device->use_llvm ? "LLVM" : "ACO",
                shader->ir_string);
        fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 
@@ -672,3 +679,58 @@ fail:
        close(fd);
        unlink(path);
 }
+
+bool
+radv_trap_handler_init(struct radv_device *device)
+{
+       struct radeon_winsys *ws = device->ws;
+
+       /* Create the trap handler shader and upload it like other shaders. */
+       device->trap_handler_shader = radv_create_trap_handler_shader(device);
+       if (!device->trap_handler_shader) {
+               fprintf(stderr, "radv: failed to create the trap handler shader.\n");
+               return false;
+       }
+
+       device->tma_bo = ws->buffer_create(ws, TMA_BO_SIZE, 8,
+                                          RADEON_DOMAIN_VRAM,
+                                          RADEON_FLAG_CPU_ACCESS |
+                                          RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                                          RADEON_FLAG_ZERO_VRAM,
+                                          RADV_BO_PRIORITY_SCRATCH);
+       if (!device->tma_bo)
+               return false;
+
+       device->tma_ptr = ws->buffer_map(device->tma_bo);
+       if (!device->tma_ptr)
+               return false;
+
+       /* Upload a buffer descriptor to store various info from the trap. */
+       uint64_t tma_va = radv_buffer_get_va(device->tma_bo) + 16;
+       uint32_t desc[4];
+
+       desc[0] = tma_va;
+       desc[1] = S_008F04_BASE_ADDRESS_HI(tma_va >> 32);
+       desc[2] = TMA_BO_SIZE;
+       desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+                 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+                 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+                 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+                 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+
+       memcpy(device->tma_ptr, desc, sizeof(desc));
+
+       return true;
+}
+
+void
+radv_trap_handler_finish(struct radv_device *device)
+{
+       struct radeon_winsys *ws = device->ws;
+
+       if (unlikely(device->trap_handler_shader))
+               radv_shader_variant_destroy(device, device->trap_handler_shader);
+
+       if (unlikely(device->tma_bo))
+               ws->buffer_destroy(device->tma_bo);
+}