radv: only enable TC-compat HTILE for images readable by a shader

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 1842daabf68ae2ade2e8bb46eeed983f1d3fd4a3..cf35855dfee636d955f32f771a385463be2238e3 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -72,8 +72,7 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
        if (device->physical_device->rad_info.chip_class < GFX8)
                return false;
 
-       if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
-           (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+       if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
                return false;
 
        if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
@@ -82,6 +81,14 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
        if (pCreateInfo->mipLevels > 1)
                return false;
 
+       /* Do not enable TC-compatible HTILE if the image isn't readable by a
+        * shader because no texture fetches will happen.
+        */
+       if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+                                   VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+                                   VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
+               return false;
+
        /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
         * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
         */
@@ -101,10 +108,10 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
                return false;
 
        if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
-               const struct VkImageFormatListCreateInfoKHR *format_list =
-                       (const struct  VkImageFormatListCreateInfoKHR *)
+               const struct VkImageFormatListCreateInfo *format_list =
+                       (const struct  VkImageFormatListCreateInfo *)
                                vk_find_struct_const(pCreateInfo->pNext,
-                                                    IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+                                                    IMAGE_FORMAT_LIST_CREATE_INFO);
 
                /* We have to ignore the existence of the list if viewFormatCount = 0 */
                if (format_list && format_list->viewFormatCount) {
@@ -129,17 +136,14 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
 static bool
 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
 {
-       if (info->scanout)
-               return true;
-
-       if (!info->bo_metadata)
-               return false;
-
-       if (device->physical_device->rad_info.chip_class >= GFX9) {
-               return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
-       } else {
-               return info->bo_metadata->u.legacy.scanout;
+       if (info->bo_metadata) {
+               if (device->physical_device->rad_info.chip_class >= GFX9)
+                       return info->bo_metadata->u.gfx9.scanout;
+               else
+                       return info->bo_metadata->u.legacy.scanout;
        }
+
+       return info->scanout;
 }
 
 static bool
@@ -162,8 +166,7 @@ radv_use_dcc_for_image(struct radv_device *device,
                return false;
 
        /* TODO: Enable DCC for storage images. */
-       if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
-           (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+       if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
                return false;
 
        if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
@@ -196,10 +199,10 @@ radv_use_dcc_for_image(struct radv_device *device,
                                                     &blendable);
 
        if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
-               const struct VkImageFormatListCreateInfoKHR *format_list =
-                       (const struct  VkImageFormatListCreateInfoKHR *)
+               const struct VkImageFormatListCreateInfo *format_list =
+                       (const struct  VkImageFormatListCreateInfo *)
                                vk_find_struct_const(pCreateInfo->pNext,
-                                                    IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+                                                    IMAGE_FORMAT_LIST_CREATE_INFO);
 
                /* We have to ignore the existence of the list if viewFormatCount = 0 */
                if (format_list && format_list->viewFormatCount) {
@@ -528,7 +531,7 @@ radv_make_buffer_descriptor(struct radv_device *device,
                 *       else: swizzle_address >= NUM_RECORDS
                 */
                state[3] |= S_008F0C_FORMAT(fmt->img_format) |
-                           S_008F0C_OOB_SELECT(0) |
+                           S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
                            S_008F0C_RESOURCE_LEVEL(1);
        } else {
                num_format = radv_translate_buffer_numformat(desc, first_non_void);
@@ -789,7 +792,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
         */
        state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
                   S_00A010_BASE_ARRAY(first_layer);
-       state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
+       state[5] = S_00A014_ARRAY_PITCH(0) |
                   S_00A014_MAX_MIP(image->info.samples > 1 ?
                                    util_logbase2(image->info.samples) :
                                    image->info.levels - 1) |
@@ -1152,6 +1155,7 @@ radv_init_metadata(struct radv_device *device,
 
        if (device->physical_device->rad_info.chip_class >= GFX9) {
                metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+               metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
        } else {
                metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
                        RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
@@ -1747,20 +1751,6 @@ radv_image_view_init(struct radv_image_view *iview,
        }
 }
 
-bool radv_layout_has_htile(const struct radv_image *image,
-                           VkImageLayout layout,
-                          bool in_render_loop,
-                           unsigned queue_mask)
-{
-       if (radv_image_is_tc_compat_htile(image))
-               return layout != VK_IMAGE_LAYOUT_GENERAL;
-
-       return radv_image_has_htile(image) &&
-              (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
-               (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
-                queue_mask == (1u << RADV_QUEUE_GENERAL)));
-}
-
 bool radv_layout_is_htile_compressed(const struct radv_image *image,
                                      VkImageLayout layout,
                                     bool in_render_loop,
@@ -1771,6 +1761,8 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image,
 
        return radv_image_has_htile(image) &&
               (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
+               layout == VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR ||
+               layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR ||
                (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
                 queue_mask == (1u << RADV_QUEUE_GENERAL)));
 }
@@ -1874,7 +1866,9 @@ void radv_GetImageSubresourceLayout(
        struct radeon_surf *surface = &plane->surface;
 
        if (device->physical_device->rad_info.chip_class >= GFX9) {
-               pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
+               uint64_t level_offset = surface->is_linear ? surface->u.gfx9.offset[level] : 0;
+               
+               pLayout->offset = plane->offset + level_offset + surface->u.gfx9.surf_slice_size * layer;
                if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
                    image->vk_format == VK_FORMAT_R32G32B32_SINT ||
                    image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
@@ -1884,8 +1878,10 @@ void radv_GetImageSubresourceLayout(
                         */
                        pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
                } else {
+                       uint32_t pitch = surface->is_linear ? surface->u.gfx9.pitch[level] : surface->u.gfx9.surf_pitch;
+
                        assert(util_is_power_of_two_nonzero(surface->bpe));
-                       pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
+                       pLayout->rowPitch = pitch * surface->bpe;
                }
 
                pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;