radv: only enable TC-compat HTILE for images readable by a shader
[mesa.git] / src / amd / vulkan / radv_image.c
index 89925386796f3adccbcd417e4e3d5f43b4843b7b..cf35855dfee636d955f32f771a385463be2238e3 100644 (file)
@@ -81,6 +81,14 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
        if (pCreateInfo->mipLevels > 1)
                return false;
 
+       /* Do not enable TC-compatible HTILE if the image isn't readable by a
+        * shader because no texture fetches will happen.
+        */
+       if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+                                   VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+                                   VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
+               return false;
+
        /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
         * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
         */
@@ -1743,22 +1751,6 @@ radv_image_view_init(struct radv_image_view *iview,
        }
 }
 
-bool radv_layout_has_htile(const struct radv_image *image,
-                           VkImageLayout layout,
-                          bool in_render_loop,
-                           unsigned queue_mask)
-{
-       if (radv_image_is_tc_compat_htile(image))
-               return layout != VK_IMAGE_LAYOUT_GENERAL;
-
-       return radv_image_has_htile(image) &&
-              (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
-               layout == VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR ||
-               layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR ||
-               (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
-                queue_mask == (1u << RADV_QUEUE_GENERAL)));
-}
-
 bool radv_layout_is_htile_compressed(const struct radv_image *image,
                                      VkImageLayout layout,
                                     bool in_render_loop,