#include "sid.h"
#include "util/debug.h"
#include "util/u_atomic.h"
+#include "vulkan/util/vk_format.h"
+
+#include "gfx10_format_table.h"
static unsigned
radv_choose_tiling(struct radv_device *device,
if (device->physical_device->rad_info.chip_class < GFX8)
return false;
- if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
- (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
return false;
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
if (pCreateInfo->mipLevels > 1)
return false;
+ /* Do not enable TC-compatible HTILE if the image isn't readable by a
+ * shader because no texture fetches will happen.
+ */
+ if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+ VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
+ return false;
+
/* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
* tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
*/
if (pCreateInfo->samples >= 2 &&
(format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
(format == VK_FORMAT_D32_SFLOAT &&
- device->physical_device->rad_info.chip_class == GFX10)))
+ device->physical_device->rad_info.chip_class >= GFX10)))
return false;
/* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
return false;
if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
- const struct VkImageFormatListCreateInfoKHR *format_list =
- (const struct VkImageFormatListCreateInfoKHR *)
+ const struct VkImageFormatListCreateInfo *format_list =
+ (const struct VkImageFormatListCreateInfo *)
vk_find_struct_const(pCreateInfo->pNext,
- IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+ IMAGE_FORMAT_LIST_CREATE_INFO);
/* We have to ignore the existence of the list if viewFormatCount = 0 */
if (format_list && format_list->viewFormatCount) {
static bool
radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
{
- if (info->scanout)
+ if (info->bo_metadata) {
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ return info->bo_metadata->u.gfx9.scanout;
+ else
+ return info->bo_metadata->u.legacy.scanout;
+ }
+
+ return info->scanout;
+}
+
+static bool
+radv_image_use_fast_clear_for_image(const struct radv_device *device,
+ const struct radv_image *image)
+{
+ if (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS)
return true;
- if (!info->bo_metadata)
+ if (image->info.samples <= 1 &&
+ image->info.width * image->info.height <= 512 * 512) {
+ /* Do not enable CMASK or DCC for small surfaces where the cost
+ * of the eliminate pass can be higher than the benefit of fast
+ * clear. RadeonSI does this, but the image threshold is
+ * different.
+ */
return false;
-
- if (device->physical_device->rad_info.chip_class >= GFX9) {
- return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
- } else {
- return info->bo_metadata->u.legacy.scanout;
}
+
+ return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
+ (image->exclusive || image->queue_family_mask == 1);
}
static bool
return false;
/* TODO: Enable DCC for storage images. */
- if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
- (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
return false;
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
vk_format_get_plane_count(format) > 1)
return false;
+ if (!radv_image_use_fast_clear_for_image(device, image))
+ return false;
+
/* TODO: Enable DCC for mipmaps on GFX9+. */
if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
device->physical_device->rad_info.chip_class >= GFX9)
&blendable);
if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
- const struct VkImageFormatListCreateInfoKHR *format_list =
- (const struct VkImageFormatListCreateInfoKHR *)
+ const struct VkImageFormatListCreateInfo *format_list =
+ (const struct VkImageFormatListCreateInfo *)
vk_find_struct_const(pCreateInfo->pNext,
- IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+ IMAGE_FORMAT_LIST_CREATE_INFO);
/* We have to ignore the existence of the list if viewFormatCount = 0 */
if (format_list && format_list->viewFormatCount) {
return true;
}
+static inline bool
+radv_use_fmask_for_image(const struct radv_device *device,
+ const struct radv_image *image)
+{
+ return image->info.samples > 1 &&
+ ((image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
+ (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
+}
+
+static inline bool
+radv_use_htile_for_image(const struct radv_device *device,
+ const struct radv_image *image)
+{
+ return image->info.levels == 1 &&
+ ((image->info.width * image->info.height >= 8 * 8) ||
+ (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
+}
+
static bool
radv_use_tc_compat_cmask_for_image(struct radv_device *device,
struct radv_image *image)
if (device->physical_device->rad_info.chip_class >= GFX10) {
width = G_00A004_WIDTH_LO(md->metadata[3]) +
(G_00A008_WIDTH_HI(md->metadata[4]) << 2) + 1;
- height = S_00A008_HEIGHT(md->metadata[4]) + 1;
+ height = G_00A008_HEIGHT(md->metadata[4]) + 1;
} else {
width = G_008F18_WIDTH(md->metadata[4]) + 1;
height = G_008F18_HEIGHT(md->metadata[4]) + 1;
return VK_SUCCESS;
}
-static int
-radv_init_surface(struct radv_device *device,
- const struct radv_image *image,
- struct radeon_surf *surface,
- unsigned plane_id,
- const VkImageCreateInfo *pCreateInfo,
- VkFormat image_format)
+static uint32_t
+radv_get_surface_flags(struct radv_device *device,
+ const struct radv_image *image,
+ unsigned plane_id,
+ const VkImageCreateInfo *pCreateInfo,
+ VkFormat image_format)
{
+ uint32_t flags;
unsigned array_mode = radv_choose_tiling(device, pCreateInfo, image_format);
VkFormat format = vk_format_get_plane_format(image_format, plane_id);
const struct vk_format_description *desc = vk_format_description(format);
is_depth = vk_format_has_depth(desc);
is_stencil = vk_format_has_stencil(desc);
- surface->blk_w = vk_format_get_blockwidth(format);
- surface->blk_h = vk_format_get_blockheight(format);
- surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
- /* align byte per element on dword */
- if (surface->bpe == 3) {
- surface->bpe = 4;
- }
-
- surface->flags = RADEON_SURF_SET(array_mode, MODE);
+ flags = RADEON_SURF_SET(array_mode, MODE);
switch (pCreateInfo->imageType){
case VK_IMAGE_TYPE_1D:
if (pCreateInfo->arrayLayers > 1)
- surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
+ flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
else
- surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
+ flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
break;
case VK_IMAGE_TYPE_2D:
if (pCreateInfo->arrayLayers > 1)
- surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
+ flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
else
- surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+ flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
break;
case VK_IMAGE_TYPE_3D:
- surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
+ flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
break;
default:
unreachable("unhandled image type");
}
+ /* Required for clearing/initializing a specific layer on GFX8. */
+ flags |= RADEON_SURF_CONTIGUOUS_DCC_LAYERS;
+
if (is_depth) {
- surface->flags |= RADEON_SURF_ZBUFFER;
+ flags |= RADEON_SURF_ZBUFFER;
+ if (!radv_use_htile_for_image(device, image) ||
+ (device->instance->debug_flags & RADV_DEBUG_NO_HIZ))
+ flags |= RADEON_SURF_NO_HTILE;
if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
- surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
+ flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
if (is_stencil)
- surface->flags |= RADEON_SURF_SBUFFER;
+ flags |= RADEON_SURF_SBUFFER;
if (device->physical_device->rad_info.chip_class >= GFX9 &&
pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
vk_format_get_blocksizebits(image_format) == 128 &&
vk_format_is_compressed(image_format))
- surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
-
- surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
+ flags |= RADEON_SURF_NO_RENDER_TARGET;
if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
- surface->flags |= RADEON_SURF_DISABLE_DCC;
+ flags |= RADEON_SURF_DISABLE_DCC;
+
+ if (!radv_use_fmask_for_image(device, image))
+ flags |= RADEON_SURF_NO_FMASK;
- return 0;
+ return flags;
}
static inline unsigned
S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
if (device->physical_device->rad_info.chip_class >= GFX10) {
- const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
+ const struct gfx10_format *fmt = &gfx10_format_table[vk_format_to_pipe_format(vk_format)];
/* OOB_SELECT chooses the out-of-bounds check:
* - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
* else: swizzle_address >= NUM_RECORDS
*/
state[3] |= S_008F0C_FORMAT(fmt->img_format) |
- S_008F0C_OOB_SELECT(0) |
+ S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
S_008F0C_RESOURCE_LEVEL(1);
} else {
num_format = radv_translate_buffer_numformat(desc, first_non_void);
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (!disable_compression && radv_dcc_enabled(image, first_level)) {
- meta_va = gpu_address + image->dcc_offset;
+ meta_va = gpu_address + plane->surface.dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
meta_va |= dcc_tile_swizzle;
} else if (!disable_compression &&
radv_image_is_tc_compat_htile(image)) {
- meta_va = gpu_address + image->htile_offset;
+ meta_va = gpu_address + plane->surface.htile_offset;
}
if (meta_va) {
C_00A018_META_PIPE_ALIGNED;
if (meta_va) {
- struct gfx9_surf_meta_flags meta;
+ struct gfx9_surf_meta_flags meta = {
+ .rb_aligned = 1,
+ .pipe_aligned = 1,
+ };
- if (image->dcc_offset)
+ if (plane->surface.dcc_offset)
meta = plane->surface.u.gfx9.dcc;
- else
- meta = plane->surface.u.gfx9.htile;
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
C_008F24_META_PIPE_ALIGNED &
C_008F24_META_RB_ALIGNED;
if (meta_va) {
- struct gfx9_surf_meta_flags meta;
+ struct gfx9_surf_meta_flags meta = {
+ .rb_aligned = 1,
+ .pipe_aligned = 1,
+ };
- if (image->dcc_offset)
+ if (plane->surface.dcc_offset)
meta = plane->surface.u.gfx9.dcc;
- else
- meta = plane->surface.u.gfx9.htile;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
unsigned type;
desc = vk_format_description(vk_format);
- img_format = gfx10_format_table[vk_format].img_format;
+ img_format = gfx10_format_table[vk_format_to_pipe_format(vk_format)].img_format;
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
*/
state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
S_00A010_BASE_ARRAY(first_layer);
- state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
+ state[5] = S_00A014_ARRAY_PITCH(0) |
S_00A014_MAX_MIP(image->info.samples > 1 ?
util_logbase2(image->info.samples) :
image->info.levels - 1) |
assert(image->plane_count == 1);
- va = gpu_address + image->offset + image->fmask_offset;
+ va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
switch (image->info.samples) {
case 2:
fmask_state[4] = S_00A010_DEPTH(last_layer) |
S_00A010_BASE_ARRAY(first_layer);
fmask_state[5] = 0;
- fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
+ fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
fmask_state[7] = 0;
} else if (fmask_state)
memset(fmask_state, 0, 8 * 4);
state[4] |= S_008F20_DEPTH(depth - 1);
state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
- if (image->dcc_offset) {
+ if (image->planes[0].surface.dcc_offset) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
} else {
/* The last dword is unused by hw. The shader uses it to clear
assert(image->plane_count == 1);
- va = gpu_address + image->offset + image->fmask_offset;
+ va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
if (device->physical_device->rad_info.chip_class == GFX9) {
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
- fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
- S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
+ fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
+ S_008F24_META_RB_ALIGNED(1);
if (radv_image_is_tc_compat_cmask(image)) {
- va = gpu_address + image->offset + image->cmask_offset;
+ va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
if (radv_image_is_tc_compat_cmask(image)) {
- va = gpu_address + image->offset + image->cmask_offset;
+ va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[7] |= va >> 8;
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
desc[1] &= C_008F14_BASE_ADDRESS_HI;
- desc[7] = image->dcc_offset >> 8;
+ desc[7] = image->planes[0].surface.dcc_offset >> 8;
/* Dwords [2:9] contain the image descriptor. */
memcpy(&md->metadata[2], desc, sizeof(desc));
if (device->physical_device->rad_info.chip_class >= GFX9) {
metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+ metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
} else {
metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
struct radv_image *image,
uint64_t offset, uint32_t stride)
{
- struct radeon_surf *surface = &image->planes[0].surface;
- unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
-
- if (device->physical_device->rad_info.chip_class >= GFX9) {
- if (stride) {
- surface->u.gfx9.surf_pitch = stride;
- surface->u.gfx9.surf_slice_size =
- (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
- }
- surface->u.gfx9.surf_offset = offset;
- } else {
- surface->u.legacy.level[0].nblk_x = stride;
- surface->u.legacy.level[0].slice_size_dw =
- ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
-
- if (offset) {
- for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
- surface->u.legacy.level[i].offset += offset;
- }
-
- }
+ ac_surface_override_offset_stride(&device->physical_device->rad_info,
+ &image->planes[0].surface,
+ image->info.levels, offset, stride);
}
static void
-radv_image_alloc_fmask(struct radv_device *device,
- struct radv_image *image)
+radv_image_alloc_single_sample_cmask(const struct radv_device *device,
+ const struct radv_image *image,
+ struct radeon_surf *surf)
{
- unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
-
- image->fmask_offset = align64(image->size, fmask_alignment);
- image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
- image->alignment = MAX2(image->alignment, fmask_alignment);
-}
-
-static void
-radv_image_alloc_cmask(struct radv_device *device,
- struct radv_image *image)
-{
- unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
- unsigned cmask_size = image->planes[0].surface.cmask_size;
- uint32_t clear_value_size = 0;
-
- if (!cmask_size)
+ if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 ||
+ image->info.levels > 1 || image->info.depth > 1 ||
+ radv_image_has_dcc(image) ||
+ !radv_image_use_fast_clear_for_image(device, image))
return;
- assert(cmask_alignment);
+ assert(image->info.storage_samples == 1);
- image->cmask_offset = align64(image->size, cmask_alignment);
- /* + 8 for storing the clear values */
- if (!image->clear_value_offset) {
- image->clear_value_offset = image->cmask_offset + cmask_size;
- clear_value_size = 8;
- }
- image->size = image->cmask_offset + cmask_size + clear_value_size;
- image->alignment = MAX2(image->alignment, cmask_alignment);
+ surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
+ surf->total_size = surf->cmask_offset + surf->cmask_size;
+ surf->alignment = MAX2(surf->alignment, surf->cmask_alignment);
}
static void
-radv_image_alloc_dcc(struct radv_image *image)
+radv_image_alloc_values(const struct radv_device *device, struct radv_image *image)
{
- assert(image->plane_count == 1);
+ if (radv_image_has_dcc(image)) {
+ image->fce_pred_offset = image->size;
+ image->size += 8 * image->info.levels;
- image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
- /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
- image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
- image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
- image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
- image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
- image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
-}
+ image->dcc_pred_offset = image->size;
+ image->size += 8 * image->info.levels;
+ }
-static void
-radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
-{
- image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
+ if (radv_image_has_dcc(image) || radv_image_has_cmask(image) ||
+ radv_image_has_htile(image)) {
+ image->clear_value_offset = image->size;
+ image->size += 8 * image->info.levels;
+ }
- /* + 8 for storing the clear values */
- image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
- image->size = image->clear_value_offset + image->info.levels * 8;
if (radv_image_is_tc_compat_htile(image) &&
device->physical_device->rad_info.has_tc_compat_zrange_bug) {
/* Metadata for the TC-compatible HTILE hardware bug which
* fast depth clears to 0.0f.
*/
image->tc_compat_zrange_offset = image->size;
- image->size = image->tc_compat_zrange_offset + image->info.levels * 4;
+ image->size += image->info.levels * 4;
}
- image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
}
-static inline bool
-radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
-{
- if (image->info.samples <= 1 &&
- image->info.width * image->info.height <= 512 * 512) {
- /* Do not enable CMASK or DCC for small surfaces where the cost
- * of the eliminate pass can be higher than the benefit of fast
- * clear. RadeonSI does this, but the image threshold is
- * different.
- */
- return false;
- }
-
- return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
- (image->exclusive || image->queue_family_mask == 1);
-}
-static inline bool
-radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
+static void
+radv_image_reset_layout(struct radv_image *image)
{
- if (!radv_image_can_enable_dcc_or_cmask(image) ||
- !radv_image_has_dcc(image))
- return false;
+ image->size = 0;
+ image->alignment = 1;
- /* On GFX8, DCC layers can be interleaved and it's currently only
- * enabled if slice size is equal to the per slice fast clear size
- * because the driver assumes that portions of multiple layers are
- * contiguous during fast clears.
- */
- if (image->info.array_size > 1) {
- const struct legacy_surf_level *surf_level =
- &image->planes[0].surface.u.legacy.level[0];
+ image->tc_compatible_cmask = image->tc_compatible_htile = 0;
+ image->fce_pred_offset = image->dcc_pred_offset = 0;
+ image->clear_value_offset = image->tc_compat_zrange_offset = 0;
- assert(device->physical_device->rad_info.chip_class == GFX8);
+ for (unsigned i = 0; i < image->plane_count; ++i) {
+ VkFormat format = vk_format_get_plane_format(image->vk_format, i);
- if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
- return false;
- }
+ uint32_t flags = image->planes[i].surface.flags;
+ memset(image->planes + i, 0, sizeof(image->planes[i]));
- return true;
-}
+ image->planes[i].surface.flags = flags;
+ image->planes[i].surface.blk_w = vk_format_get_blockwidth(format);
+ image->planes[i].surface.blk_h = vk_format_get_blockheight(format);
+ image->planes[i].surface.bpe = vk_format_get_blocksize(vk_format_depth_only(format));
-static inline bool
-radv_image_can_enable_cmask(struct radv_image *image)
-{
- if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
- /* Do not enable CMASK for non-MSAA images (fast color clear)
- * because 128 bit formats are not supported, but FMASK might
- * still be used.
- */
- return false;
+ /* align byte per element on dword */
+ if (image->planes[i].surface.bpe == 3) {
+ image->planes[i].surface.bpe = 4;
+ }
}
-
- return radv_image_can_enable_dcc_or_cmask(image) &&
- image->info.levels == 1 &&
- image->info.depth == 1 &&
- !image->planes[0].surface.is_linear;
-}
-
-static inline bool
-radv_image_can_enable_fmask(struct radv_image *image)
-{
- return image->info.samples > 1 && vk_format_is_color(image->vk_format);
-}
-
-static inline bool
-radv_image_can_enable_htile(struct radv_image *image)
-{
- return radv_image_has_htile(image) &&
- image->info.levels == 1 &&
- image->info.width * image->info.height >= 8 * 8;
-}
-
-static void radv_image_disable_dcc(struct radv_image *image)
-{
- for (unsigned i = 0; i < image->plane_count; ++i)
- image->planes[i].surface.dcc_size = 0;
-}
-
-static void radv_image_disable_htile(struct radv_image *image)
-{
- for (unsigned i = 0; i < image->plane_count; ++i)
- image->planes[i].surface.htile_size = 0;
}
VkResult
struct radv_image_create_info create_info,
struct radv_image *image)
{
- /* Check that we did not initialize things earlier */
- assert(!image->planes[0].surface.surf_size);
-
/* Clear the pCreateInfo pointer so we catch issues in the delayed case when we test in the
* common internal case. */
create_info.vk_info = NULL;
if (result != VK_SUCCESS)
return result;
- image->size = 0;
- image->alignment = 1;
+ radv_image_reset_layout(image);
+
for (unsigned plane = 0; plane < image->plane_count; ++plane) {
struct ac_surf_info info = image_info;
info.height /= desc->height_divisor;
}
+ if (create_info.no_metadata_planes || image->plane_count > 1) {
+ image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC |
+ RADEON_SURF_NO_FMASK |
+ RADEON_SURF_NO_HTILE;
+ }
+
device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
- image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
- image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
- image->alignment = image->planes[plane].surface.surf_alignment;
+ if (!create_info.no_metadata_planes && image->plane_count == 1)
+ radv_image_alloc_single_sample_cmask(device, image, &image->planes[plane].surface);
+
+ image->planes[plane].offset = align(image->size, image->planes[plane].surface.alignment);
+ image->size = image->planes[plane].offset + image->planes[plane].surface.total_size;
+ image->alignment = MAX2(image->alignment, image->planes[plane].surface.alignment);
image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
}
- if (!create_info.no_metadata_planes) {
- /* Try to enable DCC first. */
- if (radv_image_can_enable_dcc(device, image)) {
- radv_image_alloc_dcc(image);
- if (image->info.samples > 1) {
- /* CMASK should be enabled because DCC fast
- * clear with MSAA needs it.
- */
- assert(radv_image_can_enable_cmask(image));
- radv_image_alloc_cmask(device, image);
- }
- } else {
- /* When DCC cannot be enabled, try CMASK. */
- radv_image_disable_dcc(image);
- if (radv_image_can_enable_cmask(image)) {
- radv_image_alloc_cmask(device, image);
- }
- }
+ image->tc_compatible_cmask = radv_image_has_cmask(image) &&
+ radv_use_tc_compat_cmask_for_image(device, image);
- /* Try to enable FMASK for multisampled images. */
- if (radv_image_can_enable_fmask(image)) {
- radv_image_alloc_fmask(device, image);
+ image->tc_compatible_htile = radv_image_has_htile(image) &&
+ image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
- if (radv_use_tc_compat_cmask_for_image(device, image))
- image->tc_compatible_cmask = true;
- } else {
- /* Otherwise, try to enable HTILE for depth surfaces. */
- if (radv_image_can_enable_htile(image) &&
- !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
- image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
- radv_image_alloc_htile(device, image);
- } else {
- radv_image_disable_htile(image);
- }
- }
- } else {
- radv_image_disable_dcc(image);
- radv_image_disable_htile(image);
- }
+ radv_image_alloc_values(device, image);
assert(image->planes[0].surface.surf_size);
return VK_SUCCESS;
}
+static void
+radv_destroy_image(struct radv_device *device,
+ const VkAllocationCallbacks *pAllocator,
+ struct radv_image *image)
+{
+ if ((image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bo)
+ device->ws->buffer_destroy(image->bo);
+
+ if (image->owned_memory != VK_NULL_HANDLE) {
+ RADV_FROM_HANDLE(radv_device_memory, mem, image->owned_memory);
+ radv_free_memory(device, pAllocator, mem);
+ }
+
+ vk_object_base_finish(&image->base);
+ vk_free2(&device->vk.alloc, pAllocator, image);
+}
+
VkResult
radv_image_create(VkDevice _device,
const struct radv_image_create_info *create_info,
radv_assert(pCreateInfo->extent.height > 0);
radv_assert(pCreateInfo->extent.depth > 0);
- image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
+ image = vk_zalloc2(&device->vk.alloc, alloc, image_struct_size, 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!image)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &image->base, VK_OBJECT_TYPE_IMAGE);
+
image->type = pCreateInfo->imageType;
image->info.width = pCreateInfo->extent.width;
image->info.height = pCreateInfo->extent.height;
}
for (unsigned plane = 0; plane < image->plane_count; ++plane) {
- radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format);
+ image->planes[plane].surface.flags =
+ radv_get_surface_flags(device, image, plane, pCreateInfo, format);
}
bool delay_layout = external_info &&
image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
if (!image->bo) {
- vk_free2(&device->alloc, alloc, image);
+ radv_destroy_image(device, alloc, image);
return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
}
}
}
-bool radv_layout_has_htile(const struct radv_image *image,
- VkImageLayout layout,
- bool in_render_loop,
- unsigned queue_mask)
-{
- if (radv_image_is_tc_compat_htile(image))
- return layout != VK_IMAGE_LAYOUT_GENERAL;
-
- return radv_image_has_htile(image) &&
- (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
- queue_mask == (1u << RADV_QUEUE_GENERAL)));
-}
-
bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask)
{
- if (radv_image_is_tc_compat_htile(image))
+ if (radv_image_is_tc_compat_htile(image)) {
+ if (layout == VK_IMAGE_LAYOUT_GENERAL &&
+ !in_render_loop &&
+ !(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
+ /* It should be safe to enable TC-compat HTILE with
+ * VK_IMAGE_LAYOUT_GENERAL if we are not in a render
+ * loop and if the image doesn't have the storage bit
+ * set. This improves performance for apps that use
+ * GENERAL for the main depth pass because this allows
+ * compression and this reduces the number of
+ * decompressions from/to GENERAL.
+ */
+ return true;
+ }
+
return layout != VK_IMAGE_LAYOUT_GENERAL;
+ }
return radv_image_has_htile(image) &&
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
+ layout == VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR ||
+ layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR ||
(layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
queue_mask == (1u << RADV_QUEUE_GENERAL)));
}
bool in_render_loop,
unsigned queue_mask)
{
- return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
+ return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
+ queue_mask == (1u << RADV_QUEUE_GENERAL);
}
bool radv_layout_dcc_compressed(const struct radv_device *device,
if (!image)
return;
- if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
- device->ws->buffer_destroy(image->bo);
-
- if (image->owned_memory != VK_NULL_HANDLE)
- radv_FreeMemory(_device, image->owned_memory, pAllocator);
-
- vk_free2(&device->alloc, pAllocator, image);
+ radv_destroy_image(device, pAllocator, image);
}
void radv_GetImageSubresourceLayout(
struct radeon_surf *surface = &plane->surface;
if (device->physical_device->rad_info.chip_class >= GFX9) {
- pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
+ uint64_t level_offset = surface->is_linear ? surface->u.gfx9.offset[level] : 0;
+
+ pLayout->offset = plane->offset + level_offset + surface->u.gfx9.surf_slice_size * layer;
if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
image->vk_format == VK_FORMAT_R32G32B32_SINT ||
image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
*/
pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
} else {
+ uint32_t pitch = surface->is_linear ? surface->u.gfx9.pitch[level] : surface->u.gfx9.surf_pitch;
+
assert(util_is_power_of_two_nonzero(surface->bpe));
- pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
+ pLayout->rowPitch = pitch * surface->bpe;
}
pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_image_view *view;
- view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
+ view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (view == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &view->base,
+ VK_OBJECT_TYPE_IMAGE_VIEW);
+
radv_image_view_init(view, device, pCreateInfo, NULL);
*pView = radv_image_view_to_handle(view);
if (!iview)
return;
- vk_free2(&device->alloc, pAllocator, iview);
+
+ vk_object_base_finish(&iview->base);
+ vk_free2(&device->vk.alloc, pAllocator, iview);
}
void radv_buffer_view_init(struct radv_buffer_view *view,
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_buffer_view *view;
- view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
+ view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!view)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &view->base,
+ VK_OBJECT_TYPE_BUFFER_VIEW);
+
radv_buffer_view_init(view, device, pCreateInfo);
*pView = radv_buffer_view_to_handle(view);
if (!view)
return;
- vk_free2(&device->alloc, pAllocator, view);
+ vk_object_base_finish(&view->base);
+ vk_free2(&device->vk.alloc, pAllocator, view);
}
projects / mesa.git / blobdiff