radv: align the LDS size in calculate_tess_lds_size()

[mesa.git] / src / amd / vulkan / radv_meta_buffer.c

diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index 8726d36f5fa09ca123ad88e367693b2b715c27af..28343ebd83ab9b7cba822694548c93bfd7154411 100644 (file)
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -15,8 +15,8 @@ build_buffer_fill_shader(struct radv_device *dev)
        b.shader->info.cs.local_size[1] = 1;
        b.shader->info.cs.local_size[2] = 1;
 
-       nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
-       nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
+       nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -30,9 +30,10 @@ build_buffer_fill_shader(struct radv_device *dev)
        nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
                                                                  nir_intrinsic_vulkan_resource_index);
        dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+       dst_buf->num_components = 1;
        nir_intrinsic_set_desc_set(dst_buf, 0);
        nir_intrinsic_set_binding(dst_buf, 0);
-       nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
+       nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
        nir_builder_instr_insert(&b, &dst_buf->instr);
 
        nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
@@ -43,13 +44,15 @@ build_buffer_fill_shader(struct radv_device *dev)
        nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, "fill_value");
        nir_builder_instr_insert(&b, &load->instr);
 
-       nir_ssa_def *swizzled_load = nir_swizzle(&b, &load->dest.ssa, (unsigned[]) { 0, 0, 0, 0}, 4, false);
+       nir_ssa_def *swizzled_load = nir_swizzle(&b, &load->dest.ssa, (unsigned[]) { 0, 0, 0, 0}, 4);
 
        nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
        store->src[0] = nir_src_for_ssa(swizzled_load);
        store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
        store->src[2] = nir_src_for_ssa(offset);
        nir_intrinsic_set_write_mask(store, 0xf);
+       nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
+       nir_intrinsic_set_align(store, 16, 0);
        store->num_components = 4;
        nir_builder_instr_insert(&b, &store->instr);
 
@@ -67,8 +70,8 @@ build_buffer_copy_shader(struct radv_device *dev)
        b.shader->info.cs.local_size[1] = 1;
        b.shader->info.cs.local_size[2] = 1;
 
-       nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
-       nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
+       nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -82,17 +85,19 @@ build_buffer_copy_shader(struct radv_device *dev)
        nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
                                                                  nir_intrinsic_vulkan_resource_index);
        dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+       dst_buf->num_components = 1;
        nir_intrinsic_set_desc_set(dst_buf, 0);
        nir_intrinsic_set_binding(dst_buf, 0);
-       nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
+       nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
        nir_builder_instr_insert(&b, &dst_buf->instr);
 
        nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
                                                                  nir_intrinsic_vulkan_resource_index);
        src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+       src_buf->num_components = 1;
        nir_intrinsic_set_desc_set(src_buf, 0);
        nir_intrinsic_set_binding(src_buf, 1);
-       nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
+       nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL);
        nir_builder_instr_insert(&b, &src_buf->instr);
 
        nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
@@ -100,6 +105,7 @@ build_buffer_copy_shader(struct radv_device *dev)
        load->src[1] = nir_src_for_ssa(offset);
        nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
        load->num_components = 4;
+       nir_intrinsic_set_align(load, 16, 0);
        nir_builder_instr_insert(&b, &load->instr);
 
        nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
@@ -107,6 +113,8 @@ build_buffer_copy_shader(struct radv_device *dev)
        store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
        store->src[2] = nir_src_for_ssa(offset);
        nir_intrinsic_set_write_mask(store, 0xf);
+       nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
+       nir_intrinsic_set_align(store, 16, 0);
        store->num_components = 4;
        nir_builder_instr_insert(&b, &store->instr);
 
@@ -410,8 +418,8 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
        if (size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
                fill_buffer_shader(cmd_buffer, bo, offset, size, value);
                flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
-                            RADV_CMD_FLAG_INV_VMEM_L1 |
-                            RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+                            RADV_CMD_FLAG_INV_VCACHE |
+                            RADV_CMD_FLAG_WB_L2;
        } else if (size) {
                uint64_t va = radv_buffer_get_va(bo);
                va += offset;
@@ -522,7 +530,7 @@ void radv_CmdUpdateBuffer(
 
                radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0));
                radeon_emit(cmd_buffer->cs, S_370_DST_SEL(mec ?
-                                               V_370_MEM_ASYNC : V_370_MEMORY_SYNC) |
+                                               V_370_MEM : V_370_MEM_GRBM) |
                                            S_370_WR_CONFIRM(1) |
                                            S_370_ENGINE_SEL(V_370_ME));
                radeon_emit(cmd_buffer->cs, va);