radv: align the LDS size in calculate_tess_lds_size()

[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 3f214f79b92b825db4a8d2bdf28ee9f4835783ce..cc98eef0b9938308e271142a4331625792e6c938 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1173,7 +1173,7 @@ radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
        LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
        LLVMValueRef chan[4];
 
-       if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFixedVectorTypeKind) {
+       if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
                unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
 
                if (num_channels == 4 && num_channels == vec_size)
@@ -1271,7 +1271,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                 * access are detected. Only GFX6 and GFX10 are affected.
                 */
                bool unaligned_vertex_fetches = false;
-               if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
+               if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10) &&
                    vtx_info->chan_format != data_format &&
                    ((attrib_offset % vtx_info->element_size) ||
                     (attrib_stride % vtx_info->element_size)))
@@ -1282,7 +1282,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                        LLVMValueRef values[4];
 
                        assert(ctx->ac.chip_class == GFX6 ||
-                              ctx->ac.chip_class == GFX10);
+                              ctx->ac.chip_class >= GFX10);
 
                        for (unsigned chan  = 0; chan < num_channels; chan++) {
                                unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
@@ -1553,6 +1553,30 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
                        break;
                }
 
+               /* Replace NaN by zero (only 32-bit) to fix game bugs if
+                * requested.
+                */
+               if (ctx->args->options->enable_mrt_output_nan_fixup &&
+                   !is_16bit &&
+                   (col_format == V_028714_SPI_SHADER_32_R ||
+                    col_format == V_028714_SPI_SHADER_32_GR ||
+                    col_format == V_028714_SPI_SHADER_32_AR ||
+                    col_format == V_028714_SPI_SHADER_32_ABGR ||
+                    col_format == V_028714_SPI_SHADER_FP16_ABGR)) {
+                       for (unsigned i = 0; i < 4; i++) {
+                               LLVMValueRef args[2] = {
+                                       values[i],
+                                       LLVMConstInt(ctx->ac.i32, S_NAN | Q_NAN, false)
+                               };
+                               LLVMValueRef isnan =
+                                       ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f32", ctx->ac.i1,
+                                                          args, 2, AC_FUNC_ATTR_READNONE);
+                               values[i] = LLVMBuildSelect(ctx->ac.builder, isnan,
+                                                           ctx->ac.f32_0,
+                                                           values[i], "");
+                       }
+               }
+
                /* Pack f16 or norm_i16/u16. */
                if (packf) {
                        for (chan = 0; chan < 2; chan++) {
@@ -2292,8 +2316,7 @@ static void build_streamout_vertex(struct radv_shader_context *ctx,
                for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
                        unsigned output_usage_mask =
                                ctx->args->shader_info->gs.output_usage_mask[i];
-                       uint8_t output_stream =
-                               output_stream = ctx->args->shader_info->gs.output_streams[i];
+                       uint8_t output_stream = ctx->args->shader_info->gs.output_streams[i];
 
                        if (!(ctx->output_mask & (1ull << i)) ||
                            output_stream != stream)
@@ -3712,7 +3735,7 @@ ac_setup_rings(struct radv_shader_context *ctx)
 {
        if (ctx->args->options->chip_class <= GFX8 &&
            (ctx->stage == MESA_SHADER_GEOMETRY ||
-            ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
+            ctx->args->options->key.vs_common_out.as_es)) {
                unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
                                                                   : RING_ESGS_VS;
                LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
@@ -4119,8 +4142,9 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                        unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
                        unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
                        args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
-                       args->shader_info->tcs.lds_size =
+                       args->shader_info->tcs.num_lds_blocks =
                                calculate_tess_lds_size(
+                                       ctx.args->options->chip_class,
                                        ctx.args->options->key.tcs.input_vertices,
                                        ctx.shader->info.tess.tcs_vertices_out,
                                        ctx.tcs_num_inputs,
@@ -4417,8 +4441,6 @@ llvm_compile_shader(struct radv_device *device,
        tm_options |= AC_TM_SUPPORTS_SPILL;
        if (args->options->check_ir)
                tm_options |= AC_TM_CHECK_IR;
-       if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
-               tm_options |= AC_TM_NO_LOAD_STORE_OPT;
 
        thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);