radv: align the LDS size in calculate_tess_lds_size()

[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index e8ad6d83df3c0276e55752ee143850895dd2613a..cc98eef0b9938308e271142a4331625792e6c938 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1271,7 +1271,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                 * access are detected. Only GFX6 and GFX10 are affected.
                 */
                bool unaligned_vertex_fetches = false;
-               if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
+               if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10) &&
                    vtx_info->chan_format != data_format &&
                    ((attrib_offset % vtx_info->element_size) ||
                     (attrib_stride % vtx_info->element_size)))
@@ -1282,7 +1282,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                        LLVMValueRef values[4];
 
                        assert(ctx->ac.chip_class == GFX6 ||
-                              ctx->ac.chip_class == GFX10);
+                              ctx->ac.chip_class >= GFX10);
 
                        for (unsigned chan  = 0; chan < num_channels; chan++) {
                                unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
@@ -4142,8 +4142,9 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                        unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
                        unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
                        args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
-                       args->shader_info->tcs.lds_size =
+                       args->shader_info->tcs.num_lds_blocks =
                                calculate_tess_lds_size(
+                                       ctx.args->options->chip_class,
                                        ctx.args->options->key.tcs.input_vertices,
                                        ctx.shader->info.tess.tcs_vertices_out,
                                        ctx.tcs_num_inputs,
@@ -4440,8 +4441,6 @@ llvm_compile_shader(struct radv_device *device,
        tm_options |= AC_TM_SUPPORTS_SPILL;
        if (args->options->check_ir)
                tm_options |= AC_TM_CHECK_IR;
-       if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
-               tm_options |= AC_TM_NO_LOAD_STORE_OPT;
 
        thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);