#include "util/xmlconfig.h"
#include "vk_alloc.h"
#include "vk_debug_report.h"
+#include "vk_object.h"
#include "radv_radeon_winsys.h"
#include "ac_binary.h"
#define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
#endif
-
-struct gfx10_format {
- unsigned img_format:9;
-
- /* Various formats are only supported with workarounds for vertex fetch,
- * and some 32_32_32 formats are supported natively, but only for buffers
- * (possibly with some image support, actually, but no filtering). */
- bool buffers_only:1;
-};
-
-#include "gfx10_format_table.h"
-
-enum radv_mem_heap {
- RADV_MEM_HEAP_VRAM,
- RADV_MEM_HEAP_VRAM_CPU_ACCESS,
- RADV_MEM_HEAP_GTT,
- RADV_MEM_HEAP_COUNT
-};
-
-enum radv_mem_type {
- RADV_MEM_TYPE_VRAM,
- RADV_MEM_TYPE_GTT_WRITE_COMBINE,
- RADV_MEM_TYPE_VRAM_CPU_ACCESS,
- RADV_MEM_TYPE_GTT_CACHED,
- RADV_MEM_TYPE_VRAM_UNCACHED,
- RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED,
- RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED,
- RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED,
- RADV_MEM_TYPE_COUNT
-};
-
-enum radv_secure_compile_type {
- RADV_SC_TYPE_INIT_SUCCESS,
- RADV_SC_TYPE_INIT_FAILURE,
- RADV_SC_TYPE_COMPILE_PIPELINE,
- RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED,
- RADV_SC_TYPE_READ_DISK_CACHE,
- RADV_SC_TYPE_WRITE_DISK_CACHE,
- RADV_SC_TYPE_FORK_DEVICE,
- RADV_SC_TYPE_DESTROY_DEVICE,
- RADV_SC_TYPE_COUNT
-};
-
#define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
static inline uint32_t
struct radv_physical_device {
VK_LOADER_DATA _loader_data;
+ /* Link in radv_instance::physical_devices */
+ struct list_head link;
+
struct radv_instance * instance;
struct radeon_winsys *ws;
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
- /* Whether to enable the AMD_shader_ballot extension */
- bool use_shader_ballot;
-
/* Whether to enable NGG. */
bool use_ngg;
+ /* Whether to enable NGG GS. */
+ bool use_ngg_gs;
+
/* Whether to enable NGG streamout. */
bool use_ngg_streamout;
uint8_t cs_wave_size;
uint8_t ge_wave_size;
- /* Whether to use the experimental compiler backend */
- bool use_aco;
+ /* Whether to use the LLVM compiler backend */
+ bool use_llvm;
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
struct disk_cache * disk_cache;
VkPhysicalDeviceMemoryProperties memory_properties;
- enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
+ enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
+ enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
drmPciBusInfo bus_info;
};
struct radv_instance {
- VK_LOADER_DATA _loader_data;
+ struct vk_object_base base;
VkAllocationCallbacks alloc;
uint32_t apiVersion;
- int physicalDeviceCount;
- struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
char * engineName;
uint32_t engineVersion;
uint64_t debug_flags;
uint64_t perftest_flags;
- uint8_t num_sc_threads;
struct vk_debug_report_instance debug_report_callbacks;
struct radv_physical_device_dispatch_table physical_device_dispatch;
struct radv_device_dispatch_table device_dispatch;
+ bool physical_devices_enumerated;
+ struct list_head physical_devices;
+
struct driOptionCache dri_options;
struct driOptionCache available_dri_options;
-};
-static inline
-bool radv_device_use_secure_compile(struct radv_instance *instance)
-{
- return instance->num_sc_threads;
-}
+ /**
+ * Workarounds for game bugs.
+ */
+ bool enable_mrt_output_nan_fixup;
+};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
void radv_finish_wsi(struct radv_physical_device *physical_device);
struct cache_entry;
struct radv_pipeline_cache {
- struct radv_device * device;
+ struct vk_object_base base;
+ struct radv_device * device;
pthread_mutex_t mutex;
+ VkPipelineCacheCreateFlags flags;
uint32_t total_size;
uint32_t table_size;
uint32_t is_int10;
uint8_t log2_ps_iter_samples;
uint8_t num_samples;
+ bool is_dual_src;
uint32_t has_multiview_view_index : 1;
uint32_t optimisations_disabled : 1;
uint8_t topology;
#define RADV_MAX_QUEUE_FAMILIES 3
+struct radv_deferred_queue_submission;
+
enum ring_type radv_queue_family_to_ring(int f);
struct radv_queue {
struct list_head pending_submissions;
pthread_mutex_t pending_mutex;
+
+ pthread_mutex_t thread_mutex;
+ pthread_cond_t thread_cond;
+ struct radv_deferred_queue_submission *thread_submission;
+ pthread_t submission_thread;
+ bool thread_exit;
+ bool thread_running;
};
struct radv_bo_list {
pthread_mutex_t mutex;
};
-struct radv_secure_compile_process {
- /* Secure process file descriptors. Used to communicate between the
- * user facing device and the idle forked device used to fork a clean
- * process for each new pipeline compile.
- */
- int fd_secure_input;
- int fd_secure_output;
+VkResult radv_bo_list_add(struct radv_device *device,
+ struct radeon_winsys_bo *bo);
+void radv_bo_list_remove(struct radv_device *device,
+ struct radeon_winsys_bo *bo);
- /* FIFO file descriptors used to communicate between the user facing
- * device and the secure process that does the actual secure compile.
- */
- int fd_server;
- int fd_client;
+#define RADV_BORDER_COLOR_COUNT 4096
+#define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
- /* Secure compile process id */
- pid_t sc_pid;
+struct radv_device_border_color_data {
+ bool used[RADV_BORDER_COLOR_COUNT];
- /* Is the secure compile process currently in use by a thread */
- bool in_use;
-};
-
-struct radv_secure_compile_state {
- struct radv_secure_compile_process *secure_compile_processes;
- uint32_t secure_compile_thread_counter;
- mtx_t secure_compile_mutex;
+ struct radeon_winsys_bo *bo;
+ VkClearColorValue *colors_gpu_ptr;
- /* Unique process ID used to build name for FIFO file descriptor */
- char *uid;
+ /* Mutex is required to guarantee vkCreateSampler thread safety
+ * given that we are writing to a buffer and checking color occupation */
+ pthread_mutex_t mutex;
};
struct radv_device {
- VK_LOADER_DATA _loader_data;
-
- VkAllocationCallbacks alloc;
+ struct vk_device vk;
struct radv_instance * instance;
struct radeon_winsys *ws;
/* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
int force_aniso;
- struct radv_secure_compile_state *sc_state;
+ struct radv_device_border_color_data border_color_data;
/* Condition variable for legacy timelines, to notify waiters when a
* new point gets submitted. */
void *thread_trace_ptr;
uint32_t thread_trace_buffer_size;
int thread_trace_start_frame;
+
+ /* Overallocation. */
+ bool overallocation_disallowed;
+ uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
+ mtx_t overallocation_mutex;
};
struct radv_device_memory {
+ struct vk_object_base base;
struct radeon_winsys_bo *bo;
/* for dedicated allocations */
struct radv_image *image;
struct radv_buffer *buffer;
- uint32_t type_index;
- VkDeviceSize map_size;
+ uint32_t heap_index;
+ uint64_t alloc_size;
void * map;
void * user_ptr;
};
struct radv_descriptor_set {
+ struct vk_object_base base;
const struct radv_descriptor_set_layout *layout;
uint32_t size;
+ uint32_t buffer_count;
struct radeon_winsys_bo *bo;
uint64_t va;
};
struct radv_descriptor_pool {
+ struct vk_object_base base;
struct radeon_winsys_bo *bo;
uint8_t *mapped_ptr;
uint64_t current_offset;
};
struct radv_descriptor_update_template {
+ struct vk_object_base base;
uint32_t entry_count;
VkPipelineBindPoint bind_point;
struct radv_descriptor_update_template_entry entry[0];
};
struct radv_buffer {
+ struct vk_object_base base;
VkDeviceSize size;
VkBufferUsageFlags usage;
};
enum radv_dynamic_state_bits {
- RADV_DYNAMIC_VIEWPORT = 1 << 0,
- RADV_DYNAMIC_SCISSOR = 1 << 1,
- RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
- RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
- RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
- RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
- RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
- RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
- RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
- RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
- RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
- RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
- RADV_DYNAMIC_ALL = (1 << 12) - 1,
+ RADV_DYNAMIC_VIEWPORT = 1 << 0,
+ RADV_DYNAMIC_SCISSOR = 1 << 1,
+ RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
+ RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
+ RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
+ RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
+ RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
+ RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
+ RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
+ RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
+ RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
+ RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
+ RADV_DYNAMIC_CULL_MODE = 1 << 12,
+ RADV_DYNAMIC_FRONT_FACE = 1 << 13,
+ RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
+ RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
+ RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
+ RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
+ RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
+ RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
+ RADV_DYNAMIC_STENCIL_OP = 1 << 20,
+ RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
+ RADV_DYNAMIC_ALL = (1 << 22) - 1,
};
enum radv_cmd_dirty_bits {
/* Keep the dynamic state dirty bits in sync with
* enum radv_dynamic_state_bits */
- RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
- RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
- RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
- RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
- RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
- RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
- RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
- RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
- RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
- RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
- RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
- RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
- RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 12) - 1,
- RADV_CMD_DIRTY_PIPELINE = 1 << 12,
- RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 13,
- RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 14,
- RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 15,
- RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 16,
+ RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
+ RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
+ RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
+ RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
+ RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
+ RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
+ RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
+ RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
+ RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
+ RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
+ RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
+ RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
+ RADV_CMD_DIRTY_PIPELINE = 1 << 22,
+ RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
+ RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
+ RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
};
enum radv_cmd_flush_bits {
struct radv_vertex_binding {
struct radv_buffer * buffer;
VkDeviceSize offset;
+ VkDeviceSize size;
+ VkDeviceSize stride;
};
struct radv_streamout_binding {
uint32_t back;
} stencil_write_mask;
+ struct {
+ struct {
+ VkStencilOp fail_op;
+ VkStencilOp pass_op;
+ VkStencilOp depth_fail_op;
+ VkCompareOp compare_op;
+ } front;
+
+ struct {
+ VkStencilOp fail_op;
+ VkStencilOp pass_op;
+ VkStencilOp depth_fail_op;
+ VkCompareOp compare_op;
+ } back;
+ } stencil_op;
+
struct {
uint32_t front;
uint32_t back;
uint32_t factor;
uint16_t pattern;
} line_stipple;
+
+ VkCullModeFlags cull_mode;
+ VkFrontFace front_face;
+ unsigned primitive_topology;
+
+ bool depth_test_enable;
+ bool depth_write_enable;
+ VkCompareOp depth_compare_op;
+ bool depth_bounds_test_enable;
+ bool stencil_test_enable;
};
extern const struct radv_dynamic_state default_dynamic_state;
struct radv_ds_buffer_info *ds,
struct radv_image_view *iview);
-bool
-radv_sc_read(int fd, void *buf, size_t size, bool timeout);
-
/**
* Attachment state when recording a renderpass instance.
*
};
struct radv_cmd_pool {
+ struct vk_object_base base;
VkAllocationCallbacks alloc;
struct list_head cmd_buffers;
struct list_head free_cmd_buffers;
};
struct radv_cmd_buffer {
- VK_LOADER_DATA _loader_data;
+ struct vk_object_base base;
struct radv_device * device;
VkShaderStageFlags push_constant_stages;
struct radv_descriptor_set meta_push_descriptors;
- struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
+ struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
struct radv_cmd_buffer_upload upload;
bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
-void si_emit_graphics(struct radv_physical_device *physical_device,
+void si_emit_graphics(struct radv_device *device,
struct radeon_cmdbuf *cs);
void si_emit_compute(struct radv_physical_device *physical_device,
struct radeon_cmdbuf *cs);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
bool count_from_stream_output,
- uint32_t draw_vertex_count);
+ uint32_t draw_vertex_count,
+ unsigned topology);
void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
bool is_mec,
bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD);
+void radv_free_memory(struct radv_device *device,
+ const VkAllocationCallbacks* pAllocator,
+ struct radv_device_memory *mem);
static inline void
radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
uint32_t z);
struct radv_event {
+ struct vk_object_base base;
struct radeon_winsys_bo *bo;
uint64_t *map;
};
#define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
#define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
#define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
-#define RADV_HASH_SHADER_ACO (1 << 4)
+#define RADV_HASH_SHADER_LLVM (1 << 4)
void
radv_hash_shaders(unsigned char *hash,
uint32_t base;
bool partial_es_wave;
uint8_t primgroup_size;
- bool wd_switch_on_eop;
bool ia_switch_on_eoi;
bool partial_vs_wave;
};
#define SI_GS_PER_ES 128
struct radv_pipeline {
+ struct vk_object_base base;
struct radv_device * device;
struct radv_dynamic_state dynamic_state;
uint32_t vtx_base_sgpr;
struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
uint8_t vtx_emit_num;
- struct radv_prim_vertex_count prim_vertex_count;
bool can_use_guardband;
uint32_t needed_dynamic_state;
bool disable_out_of_order_rast_for_occlusion;
- uint8_t topology;
+ unsigned tess_patch_control_points;
+ unsigned pa_su_sc_mode_cntl;
+ unsigned db_depth_control;
+ bool uses_dynamic_stride;
/* Used for rbplus */
uint32_t col_format;
uint32_t cb_target_mask;
+ bool is_dual_src;
} graphics;
};
bool db_stencil_clear;
bool db_depth_disable_expclear;
bool db_stencil_disable_expclear;
- bool db_flush_depth_inplace;
- bool db_flush_stencil_inplace;
- bool db_resummarize;
+ bool depth_compress_disable;
+ bool stencil_compress_disable;
+ bool resummarize_enable;
uint32_t custom_blend_mode;
};
};
struct radv_image {
+ struct vk_object_base base;
VkImageType type;
/* The original VkFormat provided by the client. This may not match any
* of the actual surface formats.
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
- uint64_t dcc_offset;
- uint64_t htile_offset;
bool tc_compatible_htile;
bool tc_compatible_cmask;
- uint64_t cmask_offset;
- uint64_t fmask_offset;
uint64_t clear_value_offset;
uint64_t fce_pred_offset;
uint64_t dcc_pred_offset;
struct radv_image_plane planes[0];
};
-/* Whether the image has a htile that is known consistent with the contents of
- * the image. */
-bool radv_layout_has_htile(const struct radv_image *image,
- VkImageLayout layout,
- bool in_render_loop,
- unsigned queue_mask);
-
/* Whether the image has a htile that is known consistent with the contents of
* the image and is allowed to be in compressed form.
*
static inline bool
radv_image_has_cmask(const struct radv_image *image)
{
- return image->cmask_offset;
+ return image->planes[0].surface.cmask_offset;
}
/**
static inline bool
radv_image_has_fmask(const struct radv_image *image)
{
- return image->fmask_offset;
+ return image->planes[0].surface.fmask_offset;
}
/**
};
struct radv_image_view {
+ struct vk_object_base base;
struct radv_image *image; /**< VkImageViewCreateInfo::image */
struct radeon_winsys_bo *bo;
VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
struct radv_sampler_ycbcr_conversion {
+ struct vk_object_base base;
VkFormat format;
VkSamplerYcbcrModelConversion ycbcr_model;
VkSamplerYcbcrRange ycbcr_range;
};
struct radv_buffer_view {
+ struct vk_object_base base;
struct radeon_winsys_bo *bo;
VkFormat vk_format;
uint64_t range; /**< VkBufferViewCreateInfo::range */
}
struct radv_sampler {
+ struct vk_object_base base;
uint32_t state[4];
struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
+ uint32_t border_color_slot;
};
struct radv_framebuffer {
+ struct vk_object_base base;
uint32_t width;
uint32_t height;
uint32_t layers;
};
struct radv_render_pass {
+ struct vk_object_base base;
uint32_t attachment_count;
uint32_t subpass_count;
struct radv_subpass_attachment * subpass_attachments;
void radv_device_finish_meta(struct radv_device *device);
struct radv_query_pool {
+ struct vk_object_base base;
struct radeon_winsys_bo *bo;
uint32_t stride;
uint32_t availability_offset;
};
struct radv_semaphore {
+ struct vk_object_base base;
struct radv_semaphore_part permanent;
struct radv_semaphore_part temporary;
};
struct radv_image *image,
const VkImageSubresourceRange *range);
-struct radv_fence {
- struct radeon_winsys_fence *fence;
- struct wsi_fence *fence_wsi;
+typedef enum {
+ RADV_FENCE_NONE,
+ RADV_FENCE_WINSYS,
+ RADV_FENCE_SYNCOBJ,
+ RADV_FENCE_WSI,
+} radv_fence_kind;
- uint32_t syncobj;
- uint32_t temp_syncobj;
+struct radv_fence_part {
+ radv_fence_kind kind;
+
+ union {
+ /* AMDGPU winsys fence. */
+ struct radeon_winsys_fence *fence;
+
+ /* DRM syncobj handle for syncobj-based fences. */
+ uint32_t syncobj;
+
+ /* WSI fence. */
+ struct wsi_fence *fence_wsi;
+ };
+};
+
+struct radv_fence {
+ struct vk_object_base base;
+ struct radv_fence_part permanent;
+ struct radv_fence_part temporary;
};
/* radv_nir_to_llvm.c */
void radv_nir_shader_info_pass(const struct nir_shader *nir,
const struct radv_pipeline_layout *layout,
const struct radv_shader_variant_key *key,
- struct radv_shader_info *info);
+ struct radv_shader_info *info,
+ bool use_llvm);
void radv_nir_shader_info_init(struct radv_shader_info *info);
const VkRenderPassBeginInfo *pRenderPassBegin);
void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
+static inline uint32_t si_translate_prim(unsigned topology)
+{
+ switch (topology) {
+ case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
+ return V_008958_DI_PT_POINTLIST;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
+ return V_008958_DI_PT_LINELIST;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
+ return V_008958_DI_PT_LINESTRIP;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
+ return V_008958_DI_PT_TRILIST;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
+ return V_008958_DI_PT_TRISTRIP;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
+ return V_008958_DI_PT_TRIFAN;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
+ return V_008958_DI_PT_LINELIST_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
+ return V_008958_DI_PT_LINESTRIP_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
+ return V_008958_DI_PT_TRILIST_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
+ return V_008958_DI_PT_TRISTRIP_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
+ return V_008958_DI_PT_PATCH;
+ default:
+ assert(0);
+ return 0;
+ }
+}
+
+static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
+{
+ switch (op) {
+ case VK_STENCIL_OP_KEEP:
+ return V_02842C_STENCIL_KEEP;
+ case VK_STENCIL_OP_ZERO:
+ return V_02842C_STENCIL_ZERO;
+ case VK_STENCIL_OP_REPLACE:
+ return V_02842C_STENCIL_REPLACE_TEST;
+ case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
+ return V_02842C_STENCIL_ADD_CLAMP;
+ case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
+ return V_02842C_STENCIL_SUB_CLAMP;
+ case VK_STENCIL_OP_INVERT:
+ return V_02842C_STENCIL_INVERT;
+ case VK_STENCIL_OP_INCREMENT_AND_WRAP:
+ return V_02842C_STENCIL_ADD_WRAP;
+ case VK_STENCIL_OP_DECREMENT_AND_WRAP:
+ return V_02842C_STENCIL_SUB_WRAP;
+ default:
+ return 0;
+ }
+}
+
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
\
static inline struct __radv_type * \
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