gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags,
- const struct radv_pipeline_layout *layout)
+ const struct radv_pipeline_layout *layout,
+ unsigned subgroup_size, unsigned ballot_bit_size)
{
nir_shader *nir;
const nir_shader_compiler_options *nir_options =
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- if (nir->info.stage == MESA_SHADER_GEOMETRY &&
- device->physical_device->use_aco)
+ if (nir->info.stage == MESA_SHADER_GEOMETRY)
nir_lower_gs_intrinsics(nir, true);
static const nir_lower_tex_options tex_options = {
nir_remove_dead_variables(nir, nir_var_function_temp);
bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
- .subgroup_size = 64,
- .ballot_bit_size = 64,
+ .subgroup_size = subgroup_size,
+ .ballot_bit_size = ballot_bit_size,
.lower_to_scalar = 1,
.lower_subgroup_masks = 1,
.lower_shuffle = 1,
return NULL;
}
- /* Enable 64-bit and 16-bit denormals, because there is no performance
- * cost.
- *
- * If denormals are enabled, all floating-point output modifiers are
- * ignored.
- *
- * Don't enable denormals for 32-bit floats, because:
- * - Floating-point output modifiers would be ignored by the hw.
- * - Some opcodes don't support denormals, such as v_mad_f32. We would
- * have to stop using those.
- * - GFX6 & GFX7 would be very slow.
- */
- config.float_mode |= V_00B028_FP_64_DENORMS;
-
if (rtld_binary.lds_size > 0) {
unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
ac_rtld_close(&rtld_binary);
} else {
struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
- memcpy(dest_ptr, bin->data, bin->code_size);
+ memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
/* Add end-of-code markers for the UMR disassembler. */
uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
- variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
- variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
+ variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
+ variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
+
+ if (bin->stats_size) {
+ variant->statistics = calloc(bin->stats_size, 1);
+ memcpy(variant->statistics, bin->data, bin->stats_size);
+ }
}
return variant;
}
struct radv_nir_compiler_options *options,
bool gs_copy_shader,
bool keep_shader_info,
+ bool keep_statistic_info,
struct radv_shader_binary **binary_out)
{
enum radeon_family chip_family = device->physical_device->rad_info.family;
options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
options->record_ir = keep_shader_info;
+ options->record_stats = keep_statistic_info;
options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
options->address32_hi = device->physical_device->rad_info.address32_hi;
}
if (options->dump_shader) {
- fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
+ fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
+ for (int i = 1; i < shader_count; ++i)
+ fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
+
+ fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
}
struct radv_pipeline_layout *layout,
const struct radv_shader_variant_key *key,
struct radv_shader_info *info,
- bool keep_shader_info,
+ bool keep_shader_info, bool keep_statistic_info,
struct radv_shader_binary **binary_out)
{
struct radv_nir_compiler_options options = {0};
options.robust_buffer_access = device->robust_buffer_access;
return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
- &options, false, keep_shader_info, binary_out);
+ &options, false, keep_shader_info, keep_statistic_info, binary_out);
}
struct radv_shader_variant *
struct nir_shader *shader,
struct radv_shader_info *info,
struct radv_shader_binary **binary_out,
- bool keep_shader_info,
+ bool keep_shader_info, bool keep_statistic_info,
bool multiview)
{
struct radv_nir_compiler_options options = {0};
options.key.has_multiview_view_index = multiview;
return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
- info, &options, true, keep_shader_info, binary_out);
+ info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
}
void
free(variant->nir_string);
free(variant->disasm_string);
free(variant->ir_string);
+ free(variant->statistics);
free(variant);
}
"Code Size: %d bytes\n"
"LDS: %d blocks\n"
"Scratch: %d bytes per wave\n"
- "Max Waves: %d\n"
- "********************\n\n\n",
+ "Max Waves: %d\n",
conf->num_sgprs, conf->num_vgprs,
conf->spilled_sgprs, conf->spilled_vgprs,
variant->info.private_mem_vgprs, variant->exec_size,
conf->lds_size, conf->scratch_bytes_per_wave,
max_simd_waves);
+
+ if (variant->statistics) {
+ _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
+ for (unsigned i = 0; i < variant->statistics->count; i++) {
+ struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
+ uint32_t value = variant->statistics->values[i];
+ _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
+ }
+ }
+
+ _mesa_string_buffer_printf(buf, "********************\n\n\n");
}
void