#include "nir/nir_builder.h"
#include "spirv/nir_spirv.h"
-#include <llvm-c/Core.h>
-#include <llvm-c/TargetMachine.h>
-#include <llvm-c/Support.h>
-
#include "sid.h"
#include "ac_binary.h"
#include "ac_llvm_util.h"
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags,
const struct radv_pipeline_layout *layout,
- bool use_aco)
+ unsigned subgroup_size, unsigned ballot_bit_size)
{
nir_shader *nir;
- const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
- &nir_options_llvm;
+ const nir_shader_compiler_options *nir_options =
+ device->physical_device->use_aco ? &nir_options_aco :
+ &nir_options_llvm;
+
if (module->nir) {
/* Some things such as our meta clear/blit code will give us a NIR
* shader directly. In that case, we just ignore the SPIR-V entirely
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_split_per_member_structs);
- if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
+ if (nir->info.stage == MESA_SHADER_FRAGMENT &&
+ device->physical_device->use_aco)
NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
if (nir->info.stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, nir_lower_input_attachments, true);
NIR_PASS_V(nir, nir_lower_system_values);
NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
+ if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
+ NIR_PASS_V(nir, nir_lower_discard_to_demote);
}
/* Vulkan uses the separate-shader linking model */
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- if (nir->info.stage == MESA_SHADER_GEOMETRY && use_aco)
+ if (nir->info.stage == MESA_SHADER_GEOMETRY)
nir_lower_gs_intrinsics(nir, true);
static const nir_lower_tex_options tex_options = {
nir_lower_global_vars_to_local(nir);
nir_remove_dead_variables(nir, nir_var_function_temp);
+ bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
- .subgroup_size = 64,
- .ballot_bit_size = 64,
+ .subgroup_size = subgroup_size,
+ .ballot_bit_size = ballot_bit_size,
.lower_to_scalar = 1,
.lower_subgroup_masks = 1,
.lower_shuffle = 1,
.lower_shuffle_to_32bit = 1,
.lower_vote_eq_to_ballot = 1,
+ .lower_quad_broadcast_dynamic = 1,
+ .lower_quad_broadcast_dynamic_to_const = gfx7minus,
});
nir_lower_load_const_to_scalar(nir);
return NULL;
}
- /* Enable 64-bit and 16-bit denormals, because there is no performance
- * cost.
- *
- * If denormals are enabled, all floating-point output modifiers are
- * ignored.
- *
- * Don't enable denormals for 32-bit floats, because:
- * - Floating-point output modifiers would be ignored by the hw.
- * - Some opcodes don't support denormals, such as v_mad_f32. We would
- * have to stop using those.
- * - GFX6 & GFX7 would be very slow.
- */
- config.float_mode |= V_00B028_FP_64_DENORMS;
-
if (rtld_binary.lds_size > 0) {
unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
ac_rtld_close(&rtld_binary);
} else {
struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
- memcpy(dest_ptr, bin->data, bin->code_size);
+ memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
/* Add end-of-code markers for the UMR disassembler. */
uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
- variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
- variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
+ variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
+ variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
+
+ if (bin->stats_size) {
+ variant->statistics = calloc(bin->stats_size, 1);
+ memcpy(variant->statistics, bin->data, bin->stats_size);
+ }
}
return variant;
}
struct radv_nir_compiler_options *options,
bool gs_copy_shader,
bool keep_shader_info,
- bool use_aco,
+ bool keep_statistic_info,
struct radv_shader_binary **binary_out)
{
enum radeon_family chip_family = device->physical_device->rad_info.family;
options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
options->record_ir = keep_shader_info;
+ options->record_stats = keep_statistic_info;
options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
options->address32_hi = device->physical_device->rad_info.address32_hi;
shader_count >= 2 ? shaders[shader_count - 2]->info.stage
: MESA_SHADER_VERTEX);
- if (!use_aco || options->dump_shader || options->record_ir)
+ if (!device->physical_device->use_aco ||
+ options->dump_shader || options->record_ir)
ac_init_llvm_once();
- if (use_aco) {
+ if (device->physical_device->use_aco) {
aco_compile_shader(shader_count, shaders, &binary, &args);
- binary->info = *info;
} else {
- enum ac_target_machine_options tm_options = 0;
- struct ac_llvm_compiler ac_llvm;
- bool thread_compiler;
-
- tm_options |= AC_TM_SUPPORTS_SPILL;
- if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
- tm_options |= AC_TM_SISCHED;
- if (options->check_ir)
- tm_options |= AC_TM_CHECK_IR;
- if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
- tm_options |= AC_TM_NO_LOAD_STORE_OPT;
-
- thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
- radv_init_llvm_compiler(&ac_llvm,
- thread_compiler,
- chip_family, tm_options,
- info->wave_size);
-
- if (gs_copy_shader) {
- assert(shader_count == 1);
- radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
- &args);
- } else {
- radv_compile_nir_shader(&ac_llvm, &binary, &args,
- shaders, shader_count);
- }
-
- binary->info = *info;
- radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
+ llvm_compile_shader(device, shader_count, shaders, &binary, &args);
}
+ binary->info = *info;
+
struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
keep_shader_info);
if (!variant) {
free(binary);
return NULL;
}
- variant->aco_used = use_aco;
if (options->dump_shader) {
- fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
+ fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
+ for (int i = 1; i < shader_count; ++i)
+ fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
+
+ fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
}
struct radv_pipeline_layout *layout,
const struct radv_shader_variant_key *key,
struct radv_shader_info *info,
- bool keep_shader_info,
- bool use_aco,
+ bool keep_shader_info, bool keep_statistic_info,
struct radv_shader_binary **binary_out)
{
struct radv_nir_compiler_options options = {0};
if (key)
options.key = *key;
- options.explicit_scratch_args = use_aco;
+ options.explicit_scratch_args = device->physical_device->use_aco;
options.robust_buffer_access = device->robust_buffer_access;
return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
- &options, false, keep_shader_info, use_aco, binary_out);
+ &options, false, keep_shader_info, keep_statistic_info, binary_out);
}
struct radv_shader_variant *
struct nir_shader *shader,
struct radv_shader_info *info,
struct radv_shader_binary **binary_out,
- bool keep_shader_info,
- bool multiview, bool use_aco)
+ bool keep_shader_info, bool keep_statistic_info,
+ bool multiview)
{
struct radv_nir_compiler_options options = {0};
- options.explicit_scratch_args = use_aco;
+ options.explicit_scratch_args = device->physical_device->use_aco;
options.key.has_multiview_view_index = multiview;
return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
- info, &options, true, keep_shader_info, use_aco, binary_out);
+ info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
}
void
free(variant->nir_string);
free(variant->disasm_string);
free(variant->ir_string);
+ free(variant->statistics);
free(variant);
}
unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
max_simd_waves =
MIN2(max_simd_waves,
- RADV_NUM_PHYSICAL_VGPRS / vgprs);
+ device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
}
- /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
- * that PS can use.
- */
+ unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
if (lds_per_wave)
- max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
+ max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
return max_simd_waves;
}
"Code Size: %d bytes\n"
"LDS: %d blocks\n"
"Scratch: %d bytes per wave\n"
- "Max Waves: %d\n"
- "********************\n\n\n",
+ "Max Waves: %d\n",
conf->num_sgprs, conf->num_vgprs,
conf->spilled_sgprs, conf->spilled_vgprs,
variant->info.private_mem_vgprs, variant->exec_size,
conf->lds_size, conf->scratch_bytes_per_wave,
max_simd_waves);
+
+ if (variant->statistics) {
+ _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
+ for (unsigned i = 0; i < variant->statistics->count; i++) {
+ struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
+ uint32_t value = variant->statistics->values[i];
+ _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
+ }
+ }
+
+ _mesa_string_buffer_printf(buf, "********************\n\n\n");
}
void
VkShaderStatisticsInfoAMD statistics = {};
statistics.shaderStageMask = shaderStage;
- statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
+ statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
projects / mesa.git / blobdiff