bool has_multiview_view_index;
};
+enum radv_compiler_debug_level {
+ RADV_COMPILER_DEBUG_LEVEL_PERFWARN,
+ RADV_COMPILER_DEBUG_LEVEL_ERROR,
+};
+
struct radv_nir_compiler_options {
struct radv_pipeline_layout *layout;
struct radv_shader_variant_key key;
bool has_ls_vgpr_init_bug;
bool use_ngg_streamout;
bool enable_mrt_output_nan_fixup;
+ bool disable_optimizations; /* only used by ACO */
enum radeon_family family;
enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size;
uint32_t address32_hi;
+
+ struct {
+ void (*func)(void *private_data,
+ enum radv_compiler_debug_level level,
+ const char *message);
+ void *private_data;
+ } debug;
};
enum radv_ud_index {
const struct radv_shader_variant_key *key,
struct radv_shader_info *info,
bool keep_shader_info, bool keep_statistic_info,
+ bool disable_optimizations,
struct radv_shader_binary **binary_out);
struct radv_shader_variant *
struct radv_shader_info *info,
struct radv_shader_binary **binary_out,
bool multiview, bool keep_shader_info,
- bool keep_statistic_info);
+ bool keep_statistic_info,
+ bool disable_optimizations);
+
+struct radv_shader_variant *
+radv_create_trap_handler_shader(struct radv_device *device);
void
radv_shader_variant_destroy(struct radv_device *device,
radv_get_shader_name(struct radv_shader_info *info,
gl_shader_stage stage);
-void
-radv_shader_dump_stats(struct radv_device *device,
- struct radv_shader_variant *variant,
- gl_shader_stage stage,
- FILE *file);
-
bool
radv_can_dump_shader(struct radv_device *device,
struct radv_shader_module *module,
radv_can_dump_shader_stats(struct radv_device *device,
struct radv_shader_module *module);
+VkResult
+radv_dump_shader_stats(struct radv_device *device,
+ struct radv_pipeline *pipeline,
+ gl_shader_stage stage, FILE *output);
+
static inline unsigned
shader_io_get_unique_index(gl_varying_slot slot)
{