radv: dump shader stats with VK_KHR_pipeline_executable_properties

[mesa.git] / src / amd / vulkan / radv_shader.h

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 9e0a67b1378c112dcb84c506bc6c6bb9a7b9cd75..81f620140092c2006505f6165ec7aa36d00545fb 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -36,6 +36,8 @@
 #include "vulkan/vulkan.h"
 #include "vulkan/util/vk_object.h"
 
+#define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
+
 struct radv_device;
 
 struct radv_shader_module {
@@ -106,6 +108,7 @@ struct radv_fs_variant_key {
        uint8_t num_samples;
        uint32_t is_int8;
        uint32_t is_int10;
+       bool is_dual_src;
 };
 
 struct radv_cs_variant_key {
@@ -126,6 +129,11 @@ struct radv_shader_variant_key {
        bool has_multiview_view_index;
 };
 
+enum radv_compiler_debug_level {
+       RADV_COMPILER_DEBUG_LEVEL_PERFWARN,
+       RADV_COMPILER_DEBUG_LEVEL_ERROR,
+};
+
 struct radv_nir_compiler_options {
        struct radv_pipeline_layout *layout;
        struct radv_shader_variant_key key;
@@ -139,10 +147,18 @@ struct radv_nir_compiler_options {
        bool check_ir;
        bool has_ls_vgpr_init_bug;
        bool use_ngg_streamout;
+       bool enable_mrt_output_nan_fixup;
        enum radeon_family family;
        enum chip_class chip_class;
        uint32_t tess_offchip_block_dw_size;
        uint32_t address32_hi;
+
+       struct {
+               void (*func)(void *private_data,
+                            enum radv_compiler_debug_level level,
+                            const char *message);
+               void *private_data;
+       } debug;
 };
 
 enum radv_ud_index {
@@ -251,7 +267,7 @@ struct radv_shader_info {
        bool is_ngg_passthrough;
        struct {
                uint64_t ls_outputs_written;
-               uint8_t input_usage_mask[VERT_ATTRIB_MAX];
+               uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
                uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
                bool has_vertex_buffers; /* needs vertex buffers and base/start */
                bool needs_draw_id;
@@ -309,9 +325,11 @@ struct radv_shader_info {
                uint32_t explicit_shaded_mask;
                uint32_t float16_shaded_mask;
                uint32_t num_interp;
+               uint32_t cb_shader_mask;
                bool can_discard;
                bool early_fragment_test;
                bool post_depth_coverage;
+               uint8_t depth_layout;
        } ps;
        struct {
                bool uses_grid_size;
@@ -327,7 +345,7 @@ struct radv_shader_info {
                uint64_t tes_patch_inputs_read;
                unsigned tcs_vertices_out;
                uint32_t num_patches;
-               uint32_t lds_size;
+               uint32_t num_lds_blocks;
                uint8_t num_linked_inputs;
                uint8_t num_linked_outputs;
                uint8_t num_linked_patch_outputs;
@@ -435,10 +453,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
                           const struct radv_pipeline_layout *layout,
                           unsigned subgroup_size, unsigned ballot_bit_size);
 
-void *
-radv_alloc_shader_memory(struct radv_device *device,
-                         struct radv_shader_variant *shader);
-
 void
 radv_destroy_shader_slabs(struct radv_device *device);
 
@@ -474,6 +488,9 @@ radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
                           bool multiview,  bool keep_shader_info,
                           bool keep_statistic_info);
 
+struct radv_shader_variant *
+radv_create_trap_handler_shader(struct radv_device *device);
+
 void
 radv_shader_variant_destroy(struct radv_device *device,
                            struct radv_shader_variant *variant);
@@ -493,12 +510,6 @@ const char *
 radv_get_shader_name(struct radv_shader_info *info,
                     gl_shader_stage stage);
 
-void
-radv_shader_dump_stats(struct radv_device *device,
-                      struct radv_shader_variant *variant,
-                      gl_shader_stage stage,
-                      FILE *file);
-
 bool
 radv_can_dump_shader(struct radv_device *device,
                     struct radv_shader_module *module,
@@ -508,6 +519,11 @@ bool
 radv_can_dump_shader_stats(struct radv_device *device,
                           struct radv_shader_module *module);
 
+VkResult
+radv_dump_shader_stats(struct radv_device *device,
+                      struct radv_pipeline *pipeline,
+                      gl_shader_stage stage, FILE *output);
+
 static inline unsigned
 shader_io_get_unique_index(gl_varying_slot slot)
 {
@@ -533,7 +549,8 @@ shader_io_get_unique_index(gl_varying_slot slot)
 }
 
 static inline unsigned
-calculate_tess_lds_size(unsigned tcs_num_input_vertices,
+calculate_tess_lds_size(enum chip_class chip_class,
+                       unsigned tcs_num_input_vertices,
                        unsigned tcs_num_output_vertices,
                        unsigned tcs_num_inputs,
                        unsigned tcs_num_patches,
@@ -550,7 +567,17 @@ calculate_tess_lds_size(unsigned tcs_num_input_vertices,
 
        unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 
-       return output_patch0_offset + output_patch_size * tcs_num_patches;
+       unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
+
+       if (chip_class >= GFX7) {
+               assert(lds_size <= 65536);
+               lds_size = align(lds_size, 512) / 512;
+       } else {
+               assert(lds_size <= 32768);
+               lds_size = align(lds_size, 256) / 256;
+       }
+
+       return lds_size;
 }
 
 static inline unsigned