ac/gpu_info: replace num_good_cu_per_sh with min/max_good_cu_per_sa

[mesa.git] / src / amd / vulkan / si_cmd_buffer.c

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 03fa89b74c7167befa80cbef8b444b5013a32261..a43821affb22885d4c8780944eed53a9f5ed0ab4 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -164,8 +164,8 @@ si_emit_graphics(struct radv_device *device,
        int i;
 
        radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
-       radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
-       radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
+       radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
+       radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
 
        if (has_clear_state) {
                radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
@@ -293,7 +293,7 @@ si_emit_graphics(struct radv_device *device,
                }
 
                /* Compute LATE_ALLOC_VS.LIMIT. */
-               unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
+               unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
                unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
                unsigned late_alloc_wave64_gs = 0;
                unsigned cu_mask_vs = 0xffff;
@@ -456,6 +456,16 @@ si_emit_graphics(struct radv_device *device,
                radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
        }
 
+       if (device->border_color_data.bo) {
+               uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
+
+               radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
+               if (physical_device->rad_info.chip_class >= GFX7) {
+                       radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
+                                              S_028084_ADDRESS(border_color_va >> 40));
+               }
+       }
+
        if (physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
                                       S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |