int i;
radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
- radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
- radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
+ radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
+ radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
if (has_clear_state) {
radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
}
/* Compute LATE_ALLOC_VS.LIMIT. */
- unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
+ unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
unsigned late_alloc_wave64_gs = 0;
unsigned cu_mask_vs = 0xffff;