#include "radv_cs.h"
#include "sid.h"
#include "radv_util.h"
-#include "main/macros.h"
static void
si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
}
void
-si_emit_graphics(struct radv_physical_device *physical_device,
+si_emit_graphics(struct radv_device *device,
struct radeon_cmdbuf *cs)
{
+ struct radv_physical_device *physical_device = device->physical_device;
+
bool has_clear_state = physical_device->rad_info.has_clear_state;
int i;
radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
- radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
- radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
+ radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
+ radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
if (has_clear_state) {
radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
}
/* Compute LATE_ALLOC_VS.LIMIT. */
- unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
+ unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
unsigned late_alloc_wave64_gs = 0;
unsigned cu_mask_vs = 0xffff;
S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
- if (physical_device->rad_info.family == CHIP_NAVI10 ||
- physical_device->rad_info.family == CHIP_NAVI12 ||
- physical_device->rad_info.family == CHIP_NAVI14) {
+ if (physical_device->rad_info.chip_class == GFX10) {
/* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
}
+ if (device->border_color_data.bo) {
+ uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
+
+ radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
+ if (physical_device->rad_info.chip_class >= GFX7) {
+ radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
+ S_028084_ADDRESS(border_color_va >> 40));
+ }
+ }
+
if (physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
if (!cs)
return;
- si_emit_graphics(device->physical_device, cs);
+ si_emit_graphics(device, cs);
while (cs->cdw & 7) {
if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
get_viewport_xform(viewport, scale, translate);
- rect.offset.x = translate[0] - fabs(scale[0]);
- rect.offset.y = translate[1] - fabs(scale[1]);
- rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
- rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
+ rect.offset.x = translate[0] - fabsf(scale[0]);
+ rect.offset.y = translate[1] - fabsf(scale[1]);
+ rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
+ rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
return rect;
}