static struct radeon_winsys_fence *radv_amdgpu_create_fence()
{
struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
+ if (!fence)
+ return NULL;
+
fence->fence.fence = UINT64_MAX;
return (struct radeon_winsys_fence*)fence;
}
ws->cs_add_buffer(&cs->base, cs->ib_buffer);
} else {
- cs->base.buf = malloc(16384);
- cs->base.max_dw = 4096;
- if (!cs->base.buf) {
+ uint32_t *buf = malloc(16384);
+ if (!buf) {
free(cs);
return NULL;
}
+ cs->base.buf = buf;
+ cs->base.max_dw = 4096;
}
return &cs->base;
/* The maximum size in dwords has been reached,
* try to allocate a new one.
*/
- cs->old_cs_buffers =
+ struct radeon_cmdbuf *old_cs_buffers =
realloc(cs->old_cs_buffers,
- (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
- if (!cs->old_cs_buffers) {
+ (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
+ if (!old_cs_buffers) {
cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
cs->base.cdw = 0;
return;
}
+ cs->old_cs_buffers = old_cs_buffers;
/* Store the current one for submitting it later. */
cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
*cs->ib_size_ptr |= cs->base.cdw + 4;
if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
- cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
- cs->old_ib_buffers = realloc(cs->old_ib_buffers,
- cs->max_num_old_ib_buffers * sizeof(void*));
+ unsigned max_num_old_ib_buffers =
+ MAX2(1, cs->max_num_old_ib_buffers * 2);
+ struct radeon_winsys_bo **old_ib_buffers =
+ realloc(cs->old_ib_buffers,
+ max_num_old_ib_buffers * sizeof(void*));
+ if (!old_ib_buffers) {
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
+ return;
+ }
+ cs->max_num_old_ib_buffers = max_num_old_ib_buffers;
+ cs->old_ib_buffers = old_ib_buffers;
}
cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
unsigned hash;
int index = radv_amdgpu_cs_find_buffer(cs, bo);
- if (index != -1 || cs->status != VK_SUCCESS)
+ if (index != -1)
return;
if (cs->num_buffers == cs->max_num_buffers) {
if (!cs->virtual_buffer_hash_table) {
- cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
+ int *virtual_buffer_hash_table =
+ malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
+ if (!virtual_buffer_hash_table) {
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
+ return;
+ }
+ cs->virtual_buffer_hash_table = virtual_buffer_hash_table;
+
for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
cs->virtual_buffer_hash_table[i] = -1;
}
}
if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
- cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
- cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
+ unsigned max_num_virtual_buffers =
+ MAX2(2, cs->max_num_virtual_buffers * 2);
+ struct radeon_winsys_bo **virtual_buffers =
+ realloc(cs->virtual_buffers,
+ sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * max_num_virtual_buffers);
+ if (!virtual_buffers) {
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
+ return;
+ }
+ cs->max_num_virtual_buffers = max_num_virtual_buffers;
+ cs->virtual_buffers = virtual_buffers;
}
cs->virtual_buffers[cs->num_virtual_buffers] = bo;
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
+ if (cs->status != VK_SUCCESS)
+ return;
+
if (bo->is_virtual) {
radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
return;
struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
+ if (parent->status != VK_SUCCESS || child->status != VK_SUCCESS)
+ return;
+
for (unsigned i = 0; i < child->num_buffers; ++i) {
radv_amdgpu_cs_add_buffer_internal(parent,
child->handles[i].bo_handle,
r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
if (r && r == -EACCES) {
result = VK_ERROR_NOT_PERMITTED_EXT;
- goto error_create;
+ goto fail_create;
} else if (r) {
fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
result = VK_ERROR_OUT_OF_HOST_MEMORY;
- goto error_create;
+ goto fail_create;
}
ctx->ws = ws;
RADEON_FLAG_CPU_ACCESS |
RADEON_FLAG_NO_INTERPROCESS_SHARING,
RADV_BO_PRIORITY_CS);
- if (ctx->fence_bo)
- ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
- if (ctx->fence_map)
- memset(ctx->fence_map, 0, 4096);
+ if (!ctx->fence_bo) {
+ result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
+ goto fail_alloc;
+ }
+
+ ctx->fence_map = (uint64_t *)ws->base.buffer_map(ctx->fence_bo);
+ if (!ctx->fence_map) {
+ result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
+ goto fail_map;
+ }
+
+ memset(ctx->fence_map, 0, 4096);
*rctx = (struct radeon_winsys_ctx *)ctx;
return VK_SUCCESS;
-error_create:
+
+fail_map:
+ ws->base.buffer_destroy(ctx->fence_bo);
+fail_alloc:
+ amdgpu_cs_ctx_free(ctx->ctx);
+fail_create:
FREE(ctx);
return result;
}
}
static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
+ const uint32_t *syncobj_override,
struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
{
+ const uint32_t *src = syncobj_override ? syncobj_override : counts->syncobj;
struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
if (!syncobj)
return NULL;
for (unsigned i = 0; i < counts->syncobj_count; i++) {
struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
- sem->handle = counts->syncobj[i];
+ sem->handle = src[i];
}
chunk->chunk_id = chunk_id;
return syncobj;
}
+static int radv_amdgpu_cache_alloc_syncobjs(struct radv_amdgpu_winsys *ws, unsigned count, uint32_t *dst)
+{
+ pthread_mutex_lock(&ws->syncobj_lock);
+ if (count > ws->syncobj_capacity) {
+ if (ws->syncobj_capacity > UINT32_MAX / 2)
+ goto fail;
+
+ unsigned new_capacity = MAX2(count, ws->syncobj_capacity * 2);
+ uint32_t *n = realloc(ws->syncobj, new_capacity * sizeof(*ws->syncobj));
+ if (!n)
+ goto fail;
+ ws->syncobj_capacity = new_capacity;
+ ws->syncobj = n;
+ }
+
+ while(ws->syncobj_count < count) {
+ int r = amdgpu_cs_create_syncobj(ws->dev, ws->syncobj + ws->syncobj_count);
+ if (r)
+ goto fail;
+ ++ws->syncobj_count;
+ }
+
+ for (unsigned i = 0; i < count; ++i)
+ dst[i] = ws->syncobj[--ws->syncobj_count];
+
+ pthread_mutex_unlock(&ws->syncobj_lock);
+ return 0;
+
+fail:
+ pthread_mutex_unlock(&ws->syncobj_lock);
+ return -ENOMEM;
+}
+
+static void radv_amdgpu_cache_free_syncobjs(struct radv_amdgpu_winsys *ws, unsigned count, uint32_t *src)
+{
+ pthread_mutex_lock(&ws->syncobj_lock);
+
+ uint32_t cache_count = MIN2(count, UINT32_MAX - ws->syncobj_count);
+ if (cache_count + ws->syncobj_count > ws->syncobj_capacity) {
+ unsigned new_capacity = MAX2(ws->syncobj_count + cache_count, ws->syncobj_capacity * 2);
+ uint32_t* n = realloc(ws->syncobj, new_capacity * sizeof(*ws->syncobj));
+ if (n) {
+ ws->syncobj_capacity = new_capacity;
+ ws->syncobj = n;
+ }
+ }
+
+ for (unsigned i = 0; i < count; ++i) {
+ if (ws->syncobj_count < ws->syncobj_capacity)
+ ws->syncobj[ws->syncobj_count++] = src[i];
+ else
+ amdgpu_cs_destroy_syncobj(ws->dev, src[i]);
+ }
+
+ pthread_mutex_unlock(&ws->syncobj_lock);
+
+}
+
+static int radv_amdgpu_cs_prepare_syncobjs(struct radv_amdgpu_winsys *ws,
+ struct radv_winsys_sem_counts *counts,
+ uint32_t **out_syncobjs)
+{
+ int r = 0;
+
+ if (!ws->info.has_timeline_syncobj || !counts->syncobj_count) {
+ *out_syncobjs = NULL;
+ return 0;
+ }
+
+ *out_syncobjs = malloc(counts->syncobj_count * sizeof(**out_syncobjs));
+ if (!*out_syncobjs)
+ return -ENOMEM;
+
+ r = radv_amdgpu_cache_alloc_syncobjs(ws, counts->syncobj_count, *out_syncobjs);
+ if (r)
+ return r;
+
+ for (unsigned i = 0; i < counts->syncobj_count; ++i) {
+ r = amdgpu_cs_syncobj_transfer(ws->dev, (*out_syncobjs)[i], 0, counts->syncobj[i], 0, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT);
+ if (r)
+ goto fail;
+ }
+
+ r = amdgpu_cs_syncobj_reset(ws->dev, counts->syncobj, counts->syncobj_reset_count);
+ if (r)
+ goto fail;
+
+ return 0;
+fail:
+ radv_amdgpu_cache_free_syncobjs(ws, counts->syncobj_count, *out_syncobjs);
+ free(*out_syncobjs);
+ *out_syncobjs = NULL;
+ return r;
+}
+
static VkResult
radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
struct radv_amdgpu_cs_request *request,
struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
bool use_bo_list_create = ctx->ws->info.drm_minor < 27;
struct drm_amdgpu_bo_list_in bo_list_in;
+ uint32_t *in_syncobjs = NULL;
int i;
struct amdgpu_cs_fence *sem;
uint32_t bo_list = 0;
}
if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
+ r = radv_amdgpu_cs_prepare_syncobjs(ctx->ws, &sem_info->wait, &in_syncobjs);
+ if (r)
+ goto error_out;
+
wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
+ in_syncobjs,
&chunks[num_chunks],
AMDGPU_CHUNK_ID_SYNCOBJ_IN);
if (!wait_syncobj) {
if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
+ NULL,
&chunks[num_chunks],
AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
if (!signal_syncobj) {
}
error_out:
+ if (in_syncobjs) {
+ radv_amdgpu_cache_free_syncobjs(ctx->ws, sem_info->wait.syncobj_count, in_syncobjs);
+ free(in_syncobjs);
+ }
free(chunks);
free(chunk_data);
free(sem_dependencies);