<value name="Follows" value="7"/>
</enum>
- <enum name="Wrap Mode" prefix="V3D_WRAP_MODE" min_ver="41">
- <value name="Wrap mode REPEAT" value="0"/>
- <value name="Wrap mode CLAMP" value="1"/>
- <value name="Wrap mode MIRROR" value="2"/>
- <value name="Wrap mode BORDER" value="3"/>
- <value name="Wrap mode MIRROR_ONCE" value="4"/>
+ <enum name="Wrap Mode" prefix="V3D_WRAP_MODE">
+ <value name="REPEAT" value="0"/>
+ <value name="CLAMP" value="1"/>
+ <value name="MIRROR" value="2"/>
+ <value name="BORDER" value="3"/>
+ <value name="MIRROR_ONCE" value="4"/>
</enum>
<enum name="TMU Op" prefix="V3D_TMU_OP" min_ver="41">
<value name="int" value="3" min_ver="42"/> <!-- clamp to integer RT's range -->
</enum>
+ <!---
+ CL cache flush commands are not fully documented and subject to a
+ number of hardware issues that make them unreliable. Specifically:
+
+ * The L2T flush command has a 'deferred' bit to ensure the command
+ doesn't execute until all other commands in the CL have completed,
+ which is required to achieve the expected behavior. This bit comes
+ right after the mode field.
+
+ * GFXH-1895: Overlapping write combiner flush requests from different
+ sources are not safe. If two flush requests from different sources
+ overlap, the TMU may send the done signal for the first flush back to
+ the wrong source.
+
+ * GFXH-1888: It is possible for a regular access to sneak past a
+ pending L2T flush. If an L2T flush is requested via L2TCACTL while a
+ CLE-requested flush is in progress, it is possible for a regular
+ access to sneak through in the gap between the CLE flush and the
+ L2TCACTL flush.
+
+ * GFXH-1897: Writing 0 to L2TCACTL clobbers in-progress flush status.
+ Writing 0 to TMUWCF (bit 8) clears the TMUWCF bit, even if a write
+ combiner flush is still in progress. Similarly, writing 0 to L2TFLS
+ (bit 0) clears the L2TFLS bit, even if an L2T flush is still in
+ progress. Writing 0 to L2TFLM (bits 1..2) overwrites the flush mode,
+ even if a flush is not being requested (ie 0 is being written to
+ L2TFLS). If the last flush has not yet made it through the L2T
+ arbiter, this will change the mode of that flush.
+
+ GFXH-1888 and GFXH-1897 are problematic when we don't wait for L2T
+ flushes requested via LATCACTL to complete immediately.
+
+ Because of this, the driver will do all of its flushing via the kernel
+ using L2TCACTL instead of using the CL commands.
+ -->
+ <enum name="L2T Flush Mode" prefix="L2T_FLUSH_MODE">
+ <!-- invalidates all cache lines -->
+ <value name="flush" value="0"/>
+ <!-- Invalidates dirty cachelines without writeback -->
+ <value name="clear" value="1"/>
+ <!-- Writes back dirty cachelines and marks them clean, without
+ invalidating -->
+ <value name="clean" value="2"/>
+ </enum>
+
<enum name="Output Image Format" prefix="V3D_OUTPUT_IMAGE_FORMAT">
<!--
Formats appear with their channels named from the low bits to
<value name="RGBA" value="3"/>
</enum>
+ <enum name="Pack Mode" prefix="V3D_PACK_MODE">
+ <value name="16-way" value="0"/>
+ <value name="8-way" value="1"/>
+ <value name="4-way" value="2"/>
+ <value name="1-way" value="3"/>
+ </enum>
+
+ <enum name="TCS flush mode" prefix="V3D_TCS_FLUSH_MODE">
+ <value name="fully packed" value="0"/>
+ <value name="single patch" value="1"/>
+ <value name="packed complete patches" value="2"/>
+ </enum>
+
+ <enum name="Primitve counters" prefix="V3D_PRIM_COUNTS">
+ <value name="tf_words_buffer0" value="0"/>
+ <value name="tf_words_buffer1" value="1"/>
+ <value name="tf_words_buffer2" value="2"/>
+ <value name="tf_words_buffer3" value="3"/>
+ <value name="written" value="4"/>
+ <value name="tf_written" value="5"/>
+ <value name="tf_overflow" value="6"/>
+ </enum>
+
<packet code="0" name="Halt"/>
<packet code="1" name="NOP"/>
<packet code="4" name="Flush"/>
<field name="mode" size="6" start="0" type="Primitive"/>
</packet>
+ <packet code="33" name="Indirect Indexed Instanced Prim List" cl="B" max_ver="33">
+ <field name="Stride in Multiples of 4 Bytes" size="8" start="104" type="uint"/>
+ <field name="Address of Indices List" size="32" start="72" type="address"/>
+ <field name="Address" size="32" start="40" type="address"/>
+ <field name="Enable Primitive Restarts" size="1" start="39" type="bool"/>
+ <field name="Number of Draw Indirect Indexed Records" size="31" start="8" type="uint"/>
+
+ <field name="Index type" size="2" start="6" type="uint">
+ <value name="Index type 8-bit" value="0"/>
+ <value name="Index type 16-bit" value="1"/>
+ <value name="Index type 32-bit" value="2"/>
+ </field>
+
+ <field name="mode" size="6" start="0" type="Primitive"/>
+ </packet>
+
+ <packet code="33" name="Indirect Indexed Instanced Prim List" cl="B" min_ver="41">
+ <field name="Stride in Multiples of 4 Bytes" size="8" start="72" type="uint"/>
+ <field name="Address" size="32" start="40" type="address"/>
+ <field name="Enable Primitive Restarts" size="1" start="39" type="bool"/>
+ <field name="Number of Draw Indirect Indexed Records" size="31" start="8" type="uint"/>
+
+ <field name="Index type" size="2" start="6" type="uint">
+ <value name="Index type 8-bit" value="0"/>
+ <value name="Index type 16-bit" value="1"/>
+ <value name="Index type 32-bit" value="2"/>
+ </field>
+
+ <field name="mode" size="6" start="0" type="Primitive"/>
+ </packet>
+
<packet code="34" name="Indexed Instanced Prim List" cl="B" max_ver="33">
<field name="Enable Primitive Restarts" size="1" start="135" type="bool"/>
<field name="Maximum index" size="31" start="104" type="uint"/>
<field name="mode" size="8" start="0" type="Primitive"/>
</packet>
+ <packet code="37" name="Indirect Vertex Array Instanced Prims" cl="B">
+ <field name="Stride in Multiples of 4 Bytes" size="8" start="72" type="uint"/>
+ <field name="Address" size="32" start="40" type="address"/>
+ <field name="Number of Draw Indirect Array Records" size="32" start="8" type="uint"/>
+
+ <field name="mode" size="8" start="0" type="Primitive"/>
+ </packet>
+
<packet code="38" name="Vertex Array Instanced Prims" cl="B">
<field name="Index of First Vertex" size="32" start="72" type="uint"/>
<field name="Number of Instances" size="32" start="40" type="uint"/>
<field name="mode" size="8" start="0" type="Primitive"/>
</packet>
+ <packet code="39" name="Vertex Array Single Instance Prims" cl="B">
+ <field name="Index of First Vertex" size="32" start="72" type="uint"/>
+ <field name="Instance ID" size="32" start="40" type="uint"/>
+ <field name="Instance Length" size="32" start="8" type="uint"/>
+
+ <field name="mode" size="8" start="0" type="Primitive"/>
+ </packet>
+
<packet code="43" name="Base Vertex Base Instance" cl="B">
<field name="Base Instance" size="32" start="32" type="uint"/>
<field name="Size" size="32" start="32" type="uint"/>
</packet>
+ <packet code="54" name="Set InstanceID" cl="B" min_ver="41">
+ <field name="Instance ID" size="32" start="32" type="uint"/>
+ </packet>
+
+ <packet code="55" name="Set PrimitiveID" cl="B" min_ver="41">
+ <field name="Primitive ID" size="32" start="32" type="uint"/>
+ </packet>
+
<packet code="56" name="Prim List Format">
<field name="tri strip or fan" size="1" start="7" type="bool"/>
<field name="primitive type" size="6" start="0" type="uint">
</field>
</packet>
+ <packet code="57" name="Serial Number List Start">
+ <field name="address" size="26" start="6" type="address"/>
+ <field name="block size" size="2" start="0" type="uint">
+ <value name="block size 64b" value="0"/>
+ <value name="block size 128b" value="1"/>
+ <value name="block size 256b" value="2"/>
+ </field>
+ </packet>
+
<packet code="64" shortname="gl_shader" name="GL Shader State">
<field name="address" size="27" start="5" type="address"/>
<field name="number of attribute arrays" size="5" start="0" type="uint"/>
</packet>
+ <packet code="65" shortname="gl_t_shader" name="GL Shader State including TS" min_ver="41">
+ <field name="address" size="27" start="5" type="address"/>
+ <field name="number of attribute arrays" size="5" start="0" type="uint"/>
+ </packet>
+
+ <packet code="66" shortname="gl_g_shader" name="GL Shader State including GS" min_ver="41">
+ <field name="address" size="27" start="5" type="address"/>
+ <field name="number of attribute arrays" size="5" start="0" type="uint"/>
+ </packet>
+
+ <packet code="67" shortname="gl_tg_shader" name="GL Shader State including TS/GS" min_ver="41">
+ <field name="address" size="27" start="5" type="address"/>
+ <field name="number of attribute arrays" size="5" start="0" type="uint"/>
+ </packet>
+
+ <packet code="71" name="VCM Cache Size" min_ver="41">
+ <field name="Number of 16-vertex batches for rendering" size="4" start="4" type="uint"/>
+ <field name="Number of 16-vertex batches for binning" size="4" start="0" type="uint"/>
+ </packet>
+
+ <packet code="72" shortname="prim_counts_feedback" name="Primitive Counts Feedback">
+ <field name="address" size="27" start="5" type="address"/>
+ <field name="read/write 64byte" size="1" start="4" type="bool"/>
+ <field name="op" size="4" start="0" type="uint">
+ <!--
+ dword 0-3 are words written to TFB 0-3. 4 is prims generated, 5 is prims written, 6 is
+ prims overflowed
+ -->
+ <value name="store primitive counts" value="0"/>
+ <value name="store primitive counts and zero" value="1"/>
+ <!--
+ write 4 pairs of TFB state: remaining TFB space in buffer n, current address in buffer n
+ -->
+ <value name="store buffer state" value="2"/>
+ <value name="store buffer state CL" value="3"/>
+ <!--
+ Waits for buffer state stores to complete, then loads from
+ the given buffer state. This op can be offset by n to skip
+ waiting for the last n.
+ -->
+ <value name="load buffer state" value="8"/>
+ </field>
+ </packet>
+
+ <packet code="73" name="VCM Cache Size" max_ver="33">
+ <field name="Number of 16-vertex batches for rendering" size="4" start="4" type="uint"/>
+ <field name="Number of 16-vertex batches for binning" size="4" start="0" type="uint"/>
+ </packet>
+
<packet code="73" name="Transform Feedback Buffer" min_ver="41">
<field name="Buffer Address" size="32" start="32" type="address"/>
<field name="Buffer Size in 32-bit words" size="30" start="2" type="uint"/>
<packet code="75" name="Flush Transform Feedback Data"/>
+ <packet code="76" name="L1 Cache Flush Control">
+ <field name="TMU Config Cache Clear" size="4" start="12" type="uint"/>
+ <field name="TMU Data Cache Clear" size="4" start="8" type="uint"/>
+ <field name="Uniforms Cache Clear" size="4" start="4" type="uint"/>
+ <field name="Instruction Cache Clear" size="4" start="0" type="uint"/>
+ </packet>
+
+ <packet code="77" name="L2T Cache Flush Control">
+ <field name="L2T Flush Mode" size="4" start="64" type="L2T Flush Mode"/>
+ <field name="L2T Flush End" size="32" start="32" type="address"/>
+ <field name="L2T Flush Start" size="32" start="0" type="address"/>
+ </packet>
+
<struct name="Transform Feedback Output Data Spec" max_ver="33">
<field name="First Shaded Vertex Value to output" size="8" start="0" type="uint"/>
<field name="Number of consecutive Vertex Values to output as 32-bit values" size="4" start="8" type="uint" minus_one="true"/>
<packet code="120" name="Tile Binning Mode Cfg" min_ver="41">
- <field name="Height (in pixels)" size="12" start="48" type="uint" minus_one="true"/>
- <field name="Width (in pixels)" size="12" start="32" type="uint" minus_one="true"/>
+ <field name="Height (in pixels)" size="16" start="48" type="uint" minus_one="true"/>
+ <field name="Width (in pixels)" size="16" start="32" type="uint" minus_one="true"/>
<field name="Double-buffer in non-ms mode" size="1" start="15" type="bool"/>
<field name="Multisample Mode (4x)" size="1" start="14" type="bool"/>
</struct>
<struct name="Geometry Shader State Record" min_ver="41">
- <field name="Geometry Bin Mode Shader Code Address" size="32" start="0b" type="address"/>
- <field name="4-way threadable" size="1" start="0" type="bool"/>
- <field name="Start in final thread section" size="1" start="1" type="bool"/>
- <field name="Propagate NaNs" size="1" start="2" type="bool"/>
+ <field name="Geometry Bin Mode Shader Code Address" size="29" start="3" type="address"/>
+ <field name="Geometry Bin Mode Shader 4-way threadable" size="1" start="0" type="bool"/>
+ <field name="Geometry Bin Mode Shader Start in final thread section" size="1" start="1" type="bool"/>
+ <field name="Geometry Bin Mode Shader Propagate NaNs" size="1" start="2" type="bool"/>
<field name="Geometry Bin Mode Shader Uniforms Address" size="32" start="4b" type="address"/>
- <field name="Geometry Render Mode Shader Code Address" size="32" start="8b" type="address"/>
+ <field name="Geometry Render Mode Shader Code Address" size="29" start="67" type="address"/>
+ <field name="Geometry Render Mode Shader 4-way threadable" size="1" start="64" type="bool"/>
+ <field name="Geometry Render Mode Shader Start in final thread section" size="1" start="65" type="bool"/>
+ <field name="Geometry Render Mode Shader Propagate NaNs" size="1" start="66" type="bool"/>
<field name="Geometry Render Mode Shader Uniforms Address" size="32" start="12b" type="address"/>
</struct>
<struct name="Tessellation Shader State Record" min_ver="41">
- <field name="Tessellation Bin Mode Control Shader Code Address" size="32" start="0b" type="address"/>
+ <field name="Tessellation Bin Mode Control Shader Code Address" size="29" start="3" type="address"/>
+ <field name="Tessellation Bin Mode Control Shader 4-way threadable" size="1" start="0" type="bool"/>
+ <field name="Tessellation Bin Mode Control Shader Start in final thread section" size="1" start="1" type="bool"/>
+ <field name="Tessellation Bin Mode Control Shader Propagate NaNs" size="1" start="2" type="bool"/>
<field name="Tessellation Bin Mode Control Shader Uniforms Address" size="32" start="4b" type="address"/>
- <field name="Tessellation Render Mode Control Shader Code Address" size="32" start="8b" type="address"/>
+ <field name="Tessellation Render Mode Control Shader Code Address" size="29" start="67" type="address"/>
+ <field name="Tessellation Render Mode Control Shader 4-way threadable" size="1" start="64" type="bool"/>
+ <field name="Tessellation Render Mode Control Shader Start in final thread section" size="1" start="65" type="bool"/>
+ <field name="Tessellation Render Mode Control Shader Propagate NaNs" size="1" start="66" type="bool"/>
<field name="Tessellation Render Mode Control Shader Uniforms Address" size="32" start="12b" type="address"/>
- <field name="Tessellation Bin Mode Evaluation Shader Code Address" size="32" start="16b" type="address"/>
+ <field name="Tessellation Bin Mode Evaluation Shader Code Address" size="29" start="131" type="address"/>
+ <field name="Tessellation Bin Mode Evaluation Shader 4-way threadable" size="1" start="128" type="bool"/>
+ <field name="Tessellation Bin Mode Evaluation Shader Start in final thread section" size="1" start="129" type="bool"/>
+ <field name="Tessellation Bin Mode Evaluation Shader Propagate NaNs" size="1" start="130" type="bool"/>
<field name="Tessellation Bin Mode Evaluation Shader Uniforms Address" size="32" start="20b" type="address"/>
- <field name="Tessellation Render Mode Evaluation Shader Code Address" size="32" start="24b" type="address"/>
+ <field name="Tessellation Render Mode Evaluation Shader Code Address" size="29" start="195" type="address"/>
+ <field name="Tessellation Render Mode Evaluation Shader 4-way threadable" size="1" start="192" type="bool"/>
+ <field name="Tessellation Render Mode Evaluation Shader Start in final thread section" size="1" start="193" type="bool"/>
+ <field name="Tessellation Render Mode Evaluation Shader Propagate NaNs" size="1" start="194" type="bool"/>
<field name="Tessellation Render Mode Evaluation Shader Uniforms Address" size="32" start="28b" type="address"/>
</struct>
+ <struct name="Tessellation/Geometry Common Params" min_ver="41">
+ <field name="Tessellation Type" size="2" start="1" type="uint">
+ <value name="Tessellation Type Triangle" value="0"/>
+ <value name="Tessellation Type Quads" value="1"/>
+ <value name="Tessellation Type Isolines" value="2"/>
+ </field>
+
+ <field name="Tessellation point mode" size="1" start="3" type="bool"/>
+
+ <field name="Tessellation Edge Spacing" size="2" start="4" type="uint">
+ <value name="Tessellation Edge Spacing Even" value="0"/>
+ <value name="Tessellation Edge Spacing Fractional Even" value="1"/>
+ <value name="Tessellation Edge Spacing Fractional Odd" value="2"/>
+ </field>
+
+ <field name="Tessellation clockwise" size="1" start="6" type="bool"/>
+
+ <field name="Tessellation Invocations" size="5" start="12" type="uint"/> <!-- 0 == 32 -->
+
+ <field name="Geometry Shader output format" size="2" start="17" type="uint">
+ <value name="Geometry Shader Points" value="0"/>
+ <value name="Geometry Shader Line Strip" value="1"/>
+ <value name="Geometry Shader Tri Strip" value="2"/>
+ </field>
+
+ <field name="Geometry Shader Instances" size="5" start="19" type="uint"/> <!-- 0 == 32 -->
+
+ <!-- This field should not be filled, but we need it in the struct description so
+ we don't compute an incorrect packet size, since it uses an full byte.
+ -->
+ <field name="Reserved" size="8" start="24" type="uint"/>
+
+ <!-- followed by "Tessellation/Geometry Shader Params" for bin, then render -->
+ </struct>
+
+ <struct name="Tessellation/Geometry Shader Params">
+ <field name="TCS Batch Flush Mode" size="2" start="0" type="TCS flush mode"/>
+ <field name="Per-patch data column depth" size="4" start="2" type="uint"/> <!-- 8-dword units, 0==16 -->
+
+ <field name="TCS output segment size in sectors" size="6" start="8" type="uint"/>
+ <field name="TCS output segment pack mode" size="2" start="14" type="Pack Mode"/>
+
+ <field name="TES output segment size in sectors" size="6" start="16" type="uint"/>
+ <field name="TES output segment pack mode" size="2" start="22" type="Pack Mode"/>
+
+ <field name="GS output segment size in sectors" size="6" start="24" type="uint"/>
+ <field name="GS output segment pack mode" size="2" start="30" type="Pack Mode"/>
+
+ <field name="TBG max patches per TCS batch" size="4" start="32" type="uint" minus_one="true"/>
+ <field name="TBG max extra vertex segs for patches after first" size="2" start="36" type="uint"/>
+ <field name="TBG min TCS output segments required in play" size="2" start="38" type="uint" minus_one="true"/>
+ <field name="TBG min per-patch data segments required in play" size="3" start="40" type="uint" minus_one="true"/>
+ <field name="TPG max patches per TES batch" size="4" start="45" type="uint" minus_one="true"/>
+ <field name="TPG max vertex segments per TES batch" size="2" start="49" type="uint"/>
+ <field name="TPG max TCS output segments per TES batch" size="3" start="51" type="uint" minus_one="true"/>
+ <field name="TPG min TES output segments required in play" size="3" start="54" type="uint" minus_one="true"/>
+ <field name="GBG max TES output/vertex segments per GS batch" size="2" start="57" type="uint"/>
+ <field name="GBG min GS output segments required in play" size="3" start="59" type="uint" minus_one="true"/>
+ </struct>
+
<struct name="GL Shader State Attribute Record" max_ver="33">
<field name="Address" size="32" start="0" type="address"/>
<field name="Texel offset for t coordinate" size="4" start="23" type="int"/>
<field name="Texel offset for s coordinate" size="4" start="19" type="int"/>
- <field name="R Wrap Mode" size="3" start="16" type="uint">
- <value name="Wrap mode REPEAT" value="0"/>
- <value name="Wrap mode CLAMP" value="1"/>
- <value name="Wrap mode MIRROR" value="2"/>
- <value name="Wrap mode BORDER" value="3"/>
- <value name="Wrap mode MIRROR_ONCE" value="4"/>
- </field>
-
- <field name="T Wrap Mode" size="3" start="13" type="uint">
- <value name="Wrap mode REPEAT" value="0"/>
- <value name="Wrap mode CLAMP" value="1"/>
- <value name="Wrap mode MIRROR" value="2"/>
- <value name="Wrap mode BORDER" value="3"/>
- <value name="Wrap mode MIRROR_ONCE" value="4"/>
- </field>
-
- <field name="S Wrap Mode" size="3" start="10" type="uint">
- <value name="Wrap mode REPEAT" value="0"/>
- <value name="Wrap mode CLAMP" value="1"/>
- <value name="Wrap mode MIRROR" value="2"/>
- <value name="Wrap mode BORDER" value="3"/>
- <value name="Wrap mode MIRROR_ONCE" value="4"/>
- </field>
+ <field name="R Wrap Mode" size="3" start="16" type="Wrap Mode"/>
+ <field name="T Wrap Mode" size="3" start="13" type="Wrap Mode"/>
+ <field name="S Wrap Mode" size="3" start="10" type="Wrap Mode"/>
<field name="New configuration mode" size="1" start="9" type="bool" default="1"/>
</struct>
<struct name="Sampler State" min_ver="41">
- <field name="Border color Alpha" size="32" start="160" type="uint"/>
- <field name="Border color Blue" size="32" start="128" type="uint"/>
- <field name="Border color Green" size="32" start="96" type="uint"/>
- <field name="Border color Red" size="32" start="64" type="uint"/>
+ <field name="Border color word 3" size="32" start="160" type="uint"/>
+ <field name="Border color word 2" size="32" start="128" type="uint"/>
+ <field name="Border color word 1" size="32" start="96" type="uint"/>
+ <field name="Border color word 0" size="32" start="64" type="uint"/>
<field name="Maximum Anisotropy" size="2" start="61" type="uint"/>
<field name="Border Color Mode" size="3" start="58" type="Border Color Mode"/>
projects / mesa.git / blobdiff