<value name="int" value="3" min_ver="42"/> <!-- clamp to integer RT's range -->
</enum>
+ <!---
+ CL cache flush commands are not fully documented and subject to a
+ number of hardware issues that make them unreliable. Specifically:
+
+ * The L2T flush command has a 'deferred' bit to ensure the command
+ doesn't execute until all other commands in the CL have completed,
+ which is required to achieve the expected behavior. This bit comes
+ right after the mode field.
+
+ * GFXH-1895: Overlapping write combiner flush requests from different
+ sources are not safe. If two flush requests from different sources
+ overlap, the TMU may send the done signal for the first flush back to
+ the wrong source.
+
+ * GFXH-1888: It is possible for a regular access to sneak past a
+ pending L2T flush. If an L2T flush is requested via L2TCACTL while a
+ CLE-requested flush is in progress, it is possible for a regular
+ access to sneak through in the gap between the CLE flush and the
+ L2TCACTL flush.
+
+ * GFXH-1897: Writing 0 to L2TCACTL clobbers in-progress flush status.
+ Writing 0 to TMUWCF (bit 8) clears the TMUWCF bit, even if a write
+ combiner flush is still in progress. Similarly, writing 0 to L2TFLS
+ (bit 0) clears the L2TFLS bit, even if an L2T flush is still in
+ progress. Writing 0 to L2TFLM (bits 1..2) overwrites the flush mode,
+ even if a flush is not being requested (ie 0 is being written to
+ L2TFLS). If the last flush has not yet made it through the L2T
+ arbiter, this will change the mode of that flush.
+
+ GFXH-1888 and GFXH-1897 are problematic when we don't wait for L2T
+ flushes requested via LATCACTL to complete immediately.
+
+ Because of this, the driver will do all of its flushing via the kernel
+ using L2TCACTL instead of using the CL commands.
+ -->
<enum name="L2T Flush Mode" prefix="L2T_FLUSH_MODE">
<!-- invalidates all cache lines -->
<value name="flush" value="0"/>
<value name="16-way" value="0"/>
<value name="8-way" value="1"/>
<value name="4-way" value="2"/>
+ <value name="1-way" value="3"/>
</enum>
<enum name="TCS flush mode" prefix="V3D_TCS_FLUSH_MODE">
</packet>
<packet code="54" name="Set InstanceID" cl="B" min_ver="41">
- <field name="Instance ID" size="32" start="32" type="uint"/>
+ <field name="Instance ID" size="32" start="0" type="uint"/>
</packet>
<packet code="55" name="Set PrimitiveID" cl="B" min_ver="41">
- <field name="Primitive ID" size="32" start="32" type="uint"/>
+ <field name="Primitive ID" size="32" start="0" type="uint"/>
</packet>
<packet code="56" name="Prim List Format">
</struct>
<struct name="Geometry Shader State Record" min_ver="41">
- <field name="Geometry Bin Mode Shader Code Address" size="32" start="0b" type="address"/>
- <field name="4-way threadable" size="1" start="0" type="bool"/>
- <field name="Start in final thread section" size="1" start="1" type="bool"/>
- <field name="Propagate NaNs" size="1" start="2" type="bool"/>
+ <field name="Geometry Bin Mode Shader Code Address" size="29" start="3" type="address"/>
+ <field name="Geometry Bin Mode Shader 4-way threadable" size="1" start="0" type="bool"/>
+ <field name="Geometry Bin Mode Shader Start in final thread section" size="1" start="1" type="bool"/>
+ <field name="Geometry Bin Mode Shader Propagate NaNs" size="1" start="2" type="bool"/>
<field name="Geometry Bin Mode Shader Uniforms Address" size="32" start="4b" type="address"/>
- <field name="Geometry Render Mode Shader Code Address" size="32" start="8b" type="address"/>
+ <field name="Geometry Render Mode Shader Code Address" size="29" start="67" type="address"/>
+ <field name="Geometry Render Mode Shader 4-way threadable" size="1" start="64" type="bool"/>
+ <field name="Geometry Render Mode Shader Start in final thread section" size="1" start="65" type="bool"/>
+ <field name="Geometry Render Mode Shader Propagate NaNs" size="1" start="66" type="bool"/>
<field name="Geometry Render Mode Shader Uniforms Address" size="32" start="12b" type="address"/>
</struct>
<struct name="Tessellation Shader State Record" min_ver="41">
- <field name="Tessellation Bin Mode Control Shader Code Address" size="32" start="0b" type="address"/>
+ <field name="Tessellation Bin Mode Control Shader Code Address" size="29" start="3" type="address"/>
+ <field name="Tessellation Bin Mode Control Shader 4-way threadable" size="1" start="0" type="bool"/>
+ <field name="Tessellation Bin Mode Control Shader Start in final thread section" size="1" start="1" type="bool"/>
+ <field name="Tessellation Bin Mode Control Shader Propagate NaNs" size="1" start="2" type="bool"/>
<field name="Tessellation Bin Mode Control Shader Uniforms Address" size="32" start="4b" type="address"/>
- <field name="Tessellation Render Mode Control Shader Code Address" size="32" start="8b" type="address"/>
+ <field name="Tessellation Render Mode Control Shader Code Address" size="29" start="67" type="address"/>
+ <field name="Tessellation Render Mode Control Shader 4-way threadable" size="1" start="64" type="bool"/>
+ <field name="Tessellation Render Mode Control Shader Start in final thread section" size="1" start="65" type="bool"/>
+ <field name="Tessellation Render Mode Control Shader Propagate NaNs" size="1" start="66" type="bool"/>
<field name="Tessellation Render Mode Control Shader Uniforms Address" size="32" start="12b" type="address"/>
- <field name="Tessellation Bin Mode Evaluation Shader Code Address" size="32" start="16b" type="address"/>
+ <field name="Tessellation Bin Mode Evaluation Shader Code Address" size="29" start="131" type="address"/>
+ <field name="Tessellation Bin Mode Evaluation Shader 4-way threadable" size="1" start="128" type="bool"/>
+ <field name="Tessellation Bin Mode Evaluation Shader Start in final thread section" size="1" start="129" type="bool"/>
+ <field name="Tessellation Bin Mode Evaluation Shader Propagate NaNs" size="1" start="130" type="bool"/>
<field name="Tessellation Bin Mode Evaluation Shader Uniforms Address" size="32" start="20b" type="address"/>
- <field name="Tessellation Render Mode Evaluation Shader Code Address" size="32" start="24b" type="address"/>
+ <field name="Tessellation Render Mode Evaluation Shader Code Address" size="29" start="195" type="address"/>
+ <field name="Tessellation Render Mode Evaluation Shader 4-way threadable" size="1" start="192" type="bool"/>
+ <field name="Tessellation Render Mode Evaluation Shader Start in final thread section" size="1" start="193" type="bool"/>
+ <field name="Tessellation Render Mode Evaluation Shader Propagate NaNs" size="1" start="194" type="bool"/>
<field name="Tessellation Render Mode Evaluation Shader Uniforms Address" size="32" start="28b" type="address"/>
</struct>
<field name="Geometry Shader Instances" size="5" start="19" type="uint"/> <!-- 0 == 32 -->
+ <!-- This field should not be filled, but we need it in the struct description so
+ we don't compute an incorrect packet size, since it uses an full byte.
+ -->
+ <field name="Reserved" size="8" start="24" type="uint"/>
+
<!-- followed by "Tessellation/Geometry Shader Params" for bin, then render -->
</struct>
<field name="TPG max TCS output segments per TES batch" size="3" start="51" type="uint" minus_one="true"/>
<field name="TPG min TES output segments required in play" size="3" start="54" type="uint" minus_one="true"/>
<field name="GBG max TES output/vertex segments per GS batch" size="2" start="57" type="uint"/>
- <field name="GBG max TES output/vertex segments required in play" size="3" start="59" type="uint" minus_one="true"/>
+ <field name="GBG min GS output segments required in play" size="3" start="59" type="uint" minus_one="true"/>
</struct>
<struct name="GL Shader State Attribute Record" max_ver="33">
</struct>
<struct name="TMU Config Parameter 2" min_ver="41" max_ver="41">
- <field name="Pad" size="24" start="8" type="uint"/>
+ <field name="Pad" size="8" start="24" type="uint"/>
<field name="Op" size="4" start="20" type="TMU Op"/>
<field name="Offset R" size="4" start="16" type="int"/>
<field name="Offset T" size="4" start="12" type="int"/>
</struct>
<struct name="TMU Config Parameter 2" min_ver="42">
- <field name="Pad" size="23" start="9" type="uint"/>
- <field name="LOD Query" size="1" start="8" type="bool"/>
+ <field name="Pad" size="7" start="25" type="uint"/>
+ <field name="LOD Query" size="1" start="24" type="bool"/>
<field name="Op" size="4" start="20" type="TMU Op"/>
<field name="Offset R" size="4" start="16" type="int"/>
<field name="Offset T" size="4" start="12" type="int"/>
projects / mesa.git / blobdiff