v3d/compiler: fix image size for 1D arrays

[mesa.git] / src / broadcom / compiler / vir_register_allocate.c

diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c
index 1c79ac93530d0a0c40ad67e27a43a835ebff4b80..76b492d1bce99999f2e1dad2ec4cea9eaab8d518 100644 (file)
--- a/src/broadcom/compiler/vir_register_allocate.c
+++ b/src/broadcom/compiler/vir_register_allocate.c
@@ -33,14 +33,21 @@
 #define PHYS_INDEX    (ACC_INDEX + ACC_COUNT)
 #define PHYS_COUNT    64
 
+static inline bool
+qinst_writes_tmu(struct qinst *inst)
+{
+        return (inst->dst.file == QFILE_MAGIC &&
+                v3d_qpu_magic_waddr_is_tmu(inst->dst.index));
+}
+
 static bool
 is_last_ldtmu(struct qinst *inst, struct qblock *block)
 {
-        list_for_each_entry_from(struct qinst, scan_inst, inst,
+        list_for_each_entry_from(struct qinst, scan_inst, inst->link.next,
                                  &block->instructions, link) {
-                if (inst->qpu.sig.ldtmu)
+                if (scan_inst->qpu.sig.ldtmu)
                         return false;
-                if (v3d_qpu_writes_tmu(&inst->qpu))
+                if (qinst_writes_tmu(scan_inst))
                         return true;
         }
 
@@ -138,7 +145,7 @@ v3d_choose_spill_node(struct v3d_compile *c, struct ra_graph *g,
                             inst->qpu.alu.add.op == V3D_QPU_A_TMUWT)
                                 in_tmu_operation = false;
 
-                        if (v3d_qpu_writes_tmu(&inst->qpu))
+                        if (qinst_writes_tmu(inst))
                                 in_tmu_operation = true;
                 }
         }
@@ -156,7 +163,7 @@ v3d_choose_spill_node(struct v3d_compile *c, struct ra_graph *g,
 /* The spill offset for this thread takes a bit of setup, so do it once at
  * program start.
  */
-static void
+void
 v3d_setup_spill_base(struct v3d_compile *c)
 {
         c->cursor = vir_before_block(vir_entry_block(c));
@@ -185,6 +192,8 @@ v3d_setup_spill_base(struct v3d_compile *c)
         /* Make sure that we don't spill the spilling setup instructions. */
         for (int i = start_num_temps; i < c->num_temps; i++)
                 BITSET_CLEAR(c->spillable, i);
+
+        c->cursor = vir_after_block(c->cur_block);
 }
 
 static void
@@ -204,7 +213,7 @@ v3d_spill_reg(struct v3d_compile *c, int spill_temp)
         uint32_t spill_offset = 0;
 
         if (!is_uniform) {
-                uint32_t spill_offset = c->spill_size;
+                spill_offset = c->spill_size;
                 c->spill_size += V3D_CHANNELS * sizeof(uint32_t);
 
                 if (spill_offset == 0)
@@ -261,6 +270,7 @@ v3d_spill_reg(struct v3d_compile *c, int spill_temp)
                                 vir_emit_thrsw(c);
                                 vir_TMUWT(c);
                                 c->spills++;
+                                c->tmu_dirty_rcl = true;
                         }
                 }
 
@@ -299,7 +309,7 @@ struct v3d_ra_select_callback_data {
 };
 
 static unsigned int
-v3d_ra_select_callback(struct ra_graph *g, BITSET_WORD *regs, void *data)
+v3d_ra_select_callback(unsigned int n, BITSET_WORD *regs, void *data)
 {
         struct v3d_ra_select_callback_data *v3d_ra = data;
         int r5 = ACC_INDEX + 5;
@@ -668,14 +678,6 @@ v3d_register_allocate(struct v3d_compile *c, bool *spilled)
                         temp_registers[i].magic = false;
                         temp_registers[i].index = ra_reg - PHYS_INDEX;
                 }
-
-                /* If the value's never used, just write to the NOP register
-                 * for clarity in debug output.
-                 */
-                if (c->temp_start[i] == c->temp_end[i]) {
-                        temp_registers[i].magic = true;
-                        temp_registers[i].index = V3D_QPU_WADDR_NOP;
-                }
         }
 
         ralloc_free(g);