{
switch (op) {
case V3D_QPU_A_VPMSETUP:
- case V3D_QPU_A_VPMWT:
case V3D_QPU_A_LDVPMV_IN:
case V3D_QPU_A_LDVPMV_OUT:
case V3D_QPU_A_LDVPMD_IN:
{
switch (op) {
case V3D_QPU_A_VPMSETUP:
- case V3D_QPU_A_VPMWT:
case V3D_QPU_A_STVPMV:
case V3D_QPU_A_STVPMD:
case V3D_QPU_A_STVPMP:
bool
v3d_qpu_uses_sfu(const struct v3d_qpu_instr *inst)
{
- if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
- switch (inst->alu.add.op) {
- case V3D_QPU_A_RECIP:
- case V3D_QPU_A_RSQRT:
- case V3D_QPU_A_EXP:
- case V3D_QPU_A_LOG:
- case V3D_QPU_A_SIN:
- case V3D_QPU_A_RSQRT2:
- return true;
- default:
- break;
- }
+ if (v3d_qpu_instr_is_sfu(inst))
+ return true;
+ if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
return true;
return false;
}
+bool
+v3d_qpu_instr_is_sfu(const struct v3d_qpu_instr *inst)
+{
+ if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+ switch (inst->alu.add.op) {
+ case V3D_QPU_A_RECIP:
+ case V3D_QPU_A_RSQRT:
+ case V3D_QPU_A_EXP:
+ case V3D_QPU_A_LOG:
+ case V3D_QPU_A_SIN:
+ case V3D_QPU_A_RSQRT2:
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+}
+
bool
v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst)
{
v3d_qpu_magic_waddr_is_tmu(inst->alu.mul.waddr))));
}
+bool
+v3d_qpu_writes_tmu_not_tmuc(const struct v3d_qpu_instr *inst)
+{
+ return v3d_qpu_writes_tmu(inst) &&
+ (!inst->alu.add.magic_write ||
+ inst->alu.add.waddr != V3D_QPU_WADDR_TMUC) &&
+ (!inst->alu.mul.magic_write ||
+ inst->alu.mul.waddr != V3D_QPU_WADDR_TMUC);
+}
+
bool
v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst)
{
return false;
}
+static bool
+v3d_qpu_waits_vpm(const struct v3d_qpu_instr *inst)
+{
+ return inst->type == V3D_QPU_INSTR_TYPE_ALU &&
+ inst->alu.add.op == V3D_QPU_A_VPMWT;
+}
+
bool
-v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
+v3d_qpu_reads_or_writes_vpm(const struct v3d_qpu_instr *inst)
{
return v3d_qpu_reads_vpm(inst) || v3d_qpu_writes_vpm(inst);
}
+bool
+v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
+{
+ return v3d_qpu_reads_vpm(inst) ||
+ v3d_qpu_writes_vpm(inst) ||
+ v3d_qpu_waits_vpm(inst);
+}
+
bool
v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *inst)
v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *inst)
{
- if (inst->sig.ldtmu)
- return true;
-
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
(inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
}
}
- if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) &&
- inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R4) {
+ if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
+ if (inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R4)
+ return true;
+ } else if (inst->sig.ldtmu) {
return true;
}