V3D_QPU_WADDR_VPMU = 15,
V3D_QPU_WADDR_SYNC = 16,
V3D_QPU_WADDR_SYNCU = 17,
- /* reserved */
+ V3D_QPU_WADDR_SYNCB = 18,
V3D_QPU_WADDR_RECIP = 19,
V3D_QPU_WADDR_RSQRT = 20,
V3D_QPU_WADDR_EXP = 21,
V3D_QPU_WADDR_LOG = 22,
V3D_QPU_WADDR_SIN = 23,
V3D_QPU_WADDR_RSQRT2 = 24,
+ V3D_QPU_WADDR_TMUC = 32,
+ V3D_QPU_WADDR_TMUS = 33,
+ V3D_QPU_WADDR_TMUT = 34,
+ V3D_QPU_WADDR_TMUR = 35,
+ V3D_QPU_WADDR_TMUI = 36,
+ V3D_QPU_WADDR_TMUB = 37,
+ V3D_QPU_WADDR_TMUDREF = 38,
+ V3D_QPU_WADDR_TMUOFF = 39,
+ V3D_QPU_WADDR_TMUSCM = 40,
+ V3D_QPU_WADDR_TMUSF = 41,
+ V3D_QPU_WADDR_TMUSLOD = 42,
+ V3D_QPU_WADDR_TMUHS = 43,
+ V3D_QPU_WADDR_TMUHSCM = 44,
+ V3D_QPU_WADDR_TMUHSF = 45,
+ V3D_QPU_WADDR_TMUHSLOD = 46,
+ V3D_QPU_WADDR_R5REP = 55,
};
struct v3d_qpu_flags {
V3D_QPU_A_NEG,
V3D_QPU_A_FLAPUSH,
V3D_QPU_A_FLBPUSH,
- V3D_QPU_A_FLBPOP,
+ V3D_QPU_A_FLPOP,
+ V3D_QPU_A_RECIP,
V3D_QPU_A_SETMSF,
V3D_QPU_A_SETREVF,
V3D_QPU_A_NOP,
V3D_QPU_A_VDWWT,
V3D_QPU_A_IID,
V3D_QPU_A_SAMPID,
- V3D_QPU_A_PATCHID,
+ V3D_QPU_A_BARRIERID,
V3D_QPU_A_TMUWT,
V3D_QPU_A_VPMSETUP,
V3D_QPU_A_VPMWT,
V3D_QPU_A_LDVPMD_IN,
V3D_QPU_A_LDVPMD_OUT,
V3D_QPU_A_LDVPMP,
+ V3D_QPU_A_RSQRT,
+ V3D_QPU_A_EXP,
+ V3D_QPU_A_LOG,
+ V3D_QPU_A_SIN,
+ V3D_QPU_A_RSQRT2,
V3D_QPU_A_LDVPMG_IN,
V3D_QPU_A_LDVPMG_OUT,
V3D_QPU_A_FCMP,
const char *v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond);
const char *v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign);
+enum v3d_qpu_cond v3d_qpu_cond_invert(enum v3d_qpu_cond cond) ATTRIBUTE_CONST;
+
bool v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op);
bool v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op);
int v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op);
bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
+bool v3d_qpu_magic_waddr_loads_unif(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
+bool v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_instr_is_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_uses_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_tmu_not_tmuc(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
bool v3d_qpu_writes_r5(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
+bool v3d_qpu_waits_on_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux);
-bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst);
+bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_reads_flags(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_flags(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo,
const struct v3d_qpu_sig *sig) ATTRIBUTE_CONST;
+bool v3d_qpu_unpacks_f32(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_unpacks_f16(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
#endif