struct v3d_qpu_sig {
bool thrsw:1;
bool ldunif:1;
+ bool ldunifa:1;
+ bool ldunifrf:1;
+ bool ldunifarf:1;
bool ldtmu:1;
bool ldvary:1;
bool ldvpm:1;
enum v3d_qpu_instr_type type;
struct v3d_qpu_sig sig;
+ uint8_t sig_addr;
+ bool sig_magic; /* If the signal writes to a magic address */
uint8_t raddr_a;
uint8_t raddr_b;
struct v3d_qpu_flags flags;
bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
-bool v3d_qpu_writes_r3(const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
-bool v3d_qpu_writes_r4(const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
-bool v3d_qpu_writes_r5(const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
+ const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
+ const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_r5(const struct v3d_device_info *devinfo,
+ const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux);
+bool v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo,
+ const struct v3d_qpu_sig *sig) ATTRIBUTE_CONST;
#endif