SpvScope scope = SpvScopeInvocation;
SpvMemorySemanticsMask semantics = 0;
+ enum gl_access_qualifier access = 0;
+
struct vtn_value *res_val;
switch (opcode) {
case SpvOpAtomicExchange:
image = *res_val->image;
scope = vtn_constant_uint(b, w[4]);
semantics = vtn_constant_uint(b, w[5]);
+ access |= ACCESS_COHERENT;
break;
case SpvOpAtomicStore:
image = *res_val->image;
scope = vtn_constant_uint(b, w[2]);
semantics = vtn_constant_uint(b, w[3]);
+ access |= ACCESS_COHERENT;
break;
case SpvOpImageQuerySize:
* chains to find the NonUniform decoration. It's either right there or we
* can assume it doesn't exist.
*/
- enum gl_access_qualifier access = 0;
vtn_foreach_decoration(b, res_val, non_uniform_decoration_cb, &access);
nir_intrinsic_set_access(intrin, access);
nir_intrinsic_op op = get_ssbo_nir_atomic_op(b, opcode);
atomic = nir_intrinsic_instr_create(b->nb.shader, op);
+ nir_intrinsic_set_access(atomic, ACCESS_COHERENT);
+
int src = 0;
switch (opcode) {
case SpvOpAtomicLoad:
atomic = nir_intrinsic_instr_create(b->nb.shader, op);
atomic->src[0] = nir_src_for_ssa(&deref->dest.ssa);
+ if (ptr->mode != vtn_variable_mode_workgroup)
+ nir_intrinsic_set_access(atomic, ACCESS_COHERENT);
+
switch (opcode) {
case SpvOpAtomicLoad:
atomic->num_components = glsl_get_vector_elements(deref_type);
"AddressingModelPhysical32 only supported for kernels");
b->shader->info.cs.ptr_size = 32;
b->physical_ptrs = true;
- b->options->shared_addr_format = nir_address_format_32bit_global;
- b->options->global_addr_format = nir_address_format_32bit_global;
- b->options->temp_addr_format = nir_address_format_32bit_global;
+ assert(nir_address_format_bit_size(b->options->global_addr_format) == 32);
+ assert(nir_address_format_num_components(b->options->global_addr_format) == 1);
+ assert(nir_address_format_bit_size(b->options->shared_addr_format) == 32);
+ assert(nir_address_format_num_components(b->options->shared_addr_format) == 1);
+ if (!b->options->constant_as_global) {
+ assert(nir_address_format_bit_size(b->options->ubo_addr_format) == 32);
+ assert(nir_address_format_num_components(b->options->ubo_addr_format) == 1);
+ }
break;
case SpvAddressingModelPhysical64:
vtn_fail_if(b->shader->info.stage != MESA_SHADER_KERNEL,
"AddressingModelPhysical64 only supported for kernels");
b->shader->info.cs.ptr_size = 64;
b->physical_ptrs = true;
- b->options->shared_addr_format = nir_address_format_64bit_global;
- b->options->global_addr_format = nir_address_format_64bit_global;
- b->options->temp_addr_format = nir_address_format_64bit_global;
+ assert(nir_address_format_bit_size(b->options->global_addr_format) == 64);
+ assert(nir_address_format_num_components(b->options->global_addr_format) == 1);
+ assert(nir_address_format_bit_size(b->options->shared_addr_format) == 64);
+ assert(nir_address_format_num_components(b->options->shared_addr_format) == 1);
+ if (!b->options->constant_as_global) {
+ assert(nir_address_format_bit_size(b->options->ubo_addr_format) == 64);
+ assert(nir_address_format_num_components(b->options->ubo_addr_format) == 1);
+ }
break;
case SpvAddressingModelLogical:
vtn_fail_if(b->shader->info.stage == MESA_SHADER_KERNEL,
return NULL;
}
+ /* Ensure a sane address mode is being used for function temps */
+ assert(nir_address_format_bit_size(b->options->temp_addr_format) == nir_get_ptr_bitsize(b->shader));
+ assert(nir_address_format_num_components(b->options->temp_addr_format) == 1);
+
/* Set shader info defaults */
if (stage == MESA_SHADER_GEOMETRY)
b->shader->info.gs.invocations = 1;
if (entry_point->num_params && b->shader->info.stage == MESA_SHADER_KERNEL)
entry_point = vtn_emit_kernel_entry_point_wrapper(b, entry_point);
+ /* structurize the CFG */
+ nir_lower_goto_ifs(b->shader);
+
entry_point->is_entrypoint = true;
/* When multiple shader stages exist in the same SPIR-V module, we