case SpvOpBitFieldSExtract: return nir_op_ibitfield_extract;
case SpvOpBitFieldUExtract: return nir_op_ubitfield_extract;
case SpvOpBitReverse: return nir_op_bitfield_reverse;
- case SpvOpBitCount: return nir_op_bit_count;
case SpvOpUCountLeadingZerosINTEL: return nir_op_uclz;
/* SpvOpUCountTrailingZerosINTEL is handled elsewhere. */
case SpvOpFUnordEqual: return nir_op_feq;
case SpvOpINotEqual: return nir_op_ine;
case SpvOpLessOrGreater: /* Deprecated, use OrdNotEqual */
- case SpvOpFOrdNotEqual: return nir_op_fne;
- case SpvOpFUnordNotEqual: return nir_op_fne;
+ case SpvOpFOrdNotEqual: return nir_op_fneu;
+ case SpvOpFUnordNotEqual: return nir_op_fneu;
case SpvOpULessThan: return nir_op_ult;
case SpvOpSLessThan: return nir_op_ilt;
case SpvOpFOrdLessThan: return nir_op_flt;
break;
case SpvOpIsNan:
- dest->def = nir_fne(&b->nb, src[0], src[0]);
+ dest->def = nir_fneu(&b->nb, src[0], src[0]);
+ break;
+
+ case SpvOpOrdered:
+ dest->def = nir_iand(&b->nb, nir_feq(&b->nb, src[0], src[0]),
+ nir_feq(&b->nb, src[1], src[1]));
+ break;
+
+ case SpvOpUnordered:
+ dest->def = nir_ior(&b->nb, nir_fneu(&b->nb, src[0], src[0]),
+ nir_fneu(&b->nb, src[1], src[1]));
break;
case SpvOpIsInf: {
nir_ior(&b->nb,
nir_build_alu(&b->nb, op, src[0], src[1], NULL, NULL),
nir_ior(&b->nb,
- nir_fne(&b->nb, src[0], src[0]),
- nir_fne(&b->nb, src[1], src[1])));
+ nir_fneu(&b->nb, src[0], src[0]),
+ nir_fneu(&b->nb, src[1], src[1])));
break;
}
nir_imm_int(&b->nb, 32u));
break;
+ case SpvOpBitCount: {
+ /* bit_count always returns int32, but the SPIR-V opcode just says the return
+ * value needs to be big enough to store the number of bits.
+ */
+ dest->def = nir_u2u(&b->nb, nir_bit_count(&b->nb, src[0]), glsl_get_bit_size(dest_type));
+ break;
+ }
+
default: {
bool swap;
unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);