nir/vtn: SPIR-V bit count opcodes (core and extension) dest size mismatches nir

[mesa.git] / src / compiler / spirv / vtn_alu.c

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index ada56dcb67c7c2b36b8136cc00a121db77098b2e..b403a25e51b20659bc22b13fc61f32a73355427e 100644 (file)
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -257,7 +257,6 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b,
    case SpvOpBitFieldSExtract:      return nir_op_ibitfield_extract;
    case SpvOpBitFieldUExtract:      return nir_op_ubitfield_extract;
    case SpvOpBitReverse:            return nir_op_bitfield_reverse;
-   case SpvOpBitCount:              return nir_op_bit_count;
 
    case SpvOpUCountLeadingZerosINTEL: return nir_op_uclz;
    /* SpvOpUCountTrailingZerosINTEL is handled elsewhere. */
@@ -640,6 +639,14 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
                                nir_imm_int(&b->nb, 32u));
       break;
 
+   case SpvOpBitCount: {
+      /* bit_count always returns int32, but the SPIR-V opcode just says the return
+       * value needs to be big enough to store the number of bits.
+       */
+      dest->def = nir_u2u(&b->nb, nir_bit_count(&b->nb, src[0]), glsl_get_bit_size(dest_type));
+      break;
+   }
+
    default: {
       bool swap;
       unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);