freedreno/a6xx: Fix CP_BIN_SIZE_ADDRESS name

[mesa.git] / src / freedreno / .gitlab-ci / reference / crash.log

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index b1a79865cf3dfdf8aba43e5514d78063671c54b0..7f17459bf6395a96acb51c7b23f3fd3757315164 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -743,12 +743,12 @@ registers:
        00000000        CP_IB2_REM_SIZE: 0
        00000000        CP_SDS_BASE: 0
        00000000        CP_SDS_BASE_HI: 0
-       00000000        0x930: 00000000
-       0000c600        CP_BIN_SIZE_ADDRESS: 0xc600
-       00010000        CP_BIN_SIZE_ADDRESS_HI: 0x10000
-       00000000        0x933: 00000000
-       00000000        CP_BIN_DATA_ADDR: 0
-       00000000        CP_BIN_DATA_ADDR_HI: 0
+       00000000        CP_SDS_REM_SIZE: 0
+       0000c600        CP_MRB_BASE: 0xc600
+       00010000        CP_MRB_BASE_HI: 0x10000
+       00000000        CP_MRB_REM_SIZE: 0
+       00000000        CP_VSD_BASE: 0
+       00000000        CP_VSD_BASE_HI: 0
        00000000        0x936: 00000000
        00800000        0x937: 00800000
        00000000        0x938: 00000000
@@ -762,13 +762,13 @@ registers:
        0000000c        0x943: 0000000c
        00000000        0x944: 00000000
        00000000        0x945: 00000000
-       00000000        0x946: 00000000
-       00000000        0x947: 00000000
+       00000000        CP_MRB_DWORDS: 0
+       00000000        CP_VSD_DWORDS: 0
        000f0004        0x948: 000f0004
        00060002        CP_CSQ_IB1_STAT: { REM = 0x6 | 0x2 }
        00000000        CP_CSQ_IB2_STAT: { REM = 0 }
        00000000        0x94b: 00000000
-       00000000        0x94c: 00000000
+       00000000        CP_MRQ_MRB_STAT: { REM = 0 }
        00000000        0x94d: 00000000
        00305efe        CP_ALWAYS_ON_COUNTER_LO: 0x305efe
        00000000        CP_ALWAYS_ON_COUNTER_HI: 0