freedreno/computerator: Set SP_MODE_CONTROL to the same value as vulkan/GL

[mesa.git] / src / freedreno / computerator / a6xx.c

diff --git a/src/freedreno/computerator/a6xx.c b/src/freedreno/computerator/a6xx.c
index 6eff57d50ecf577d50459968ee5aa47ec42c7c90..4cd8e5784f6d0ca7d318554c6c63ae375d3282b4 100644 (file)
--- a/src/freedreno/computerator/a6xx.c
+++ b/src/freedreno/computerator/a6xx.c
@@ -25,9 +25,9 @@
 
 #include "util/u_math.h"
 
-#include "registers/adreno_pm4.xml.h"
-#include "registers/adreno_common.xml.h"
-#include "registers/a6xx.xml.h"
+#include "adreno_pm4.xml.h"
+#include "adreno_common.xml.h"
+#include "a6xx.xml.h"
 
 #include "main.h"
 #include "ir3_asm.h"
@@ -117,8 +117,18 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
        const struct ir3_info *i = &v->info;
        enum a3xx_threadsize thrsz = FOUR_QUADS;
 
-       OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
-       OUT_RING(ring, 0xff);
+       OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
+       OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
+
+       OUT_PKT4(ring, REG_A6XX_HLSQ_INVALIDATE_CMD, 1);
+       OUT_RING(ring, A6XX_HLSQ_INVALIDATE_CMD_VS_STATE |
+                   A6XX_HLSQ_INVALIDATE_CMD_HS_STATE |
+                   A6XX_HLSQ_INVALIDATE_CMD_DS_STATE |
+                   A6XX_HLSQ_INVALIDATE_CMD_GS_STATE |
+                   A6XX_HLSQ_INVALIDATE_CMD_FS_STATE |
+                   A6XX_HLSQ_INVALIDATE_CMD_CS_STATE |
+                   A6XX_HLSQ_INVALIDATE_CMD_CS_IBO |
+                   A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO);
 
        unsigned constlen = align(v->constlen, 4);
        OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
@@ -135,7 +145,8 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
        OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
        OUT_RING(ring, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
                A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
-               A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
+               A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
+               COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
                A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
                COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
 
@@ -207,7 +218,7 @@ cs_const_emit(struct fd_ringbuffer *ring, struct kernel *kernel, uint32_t grid[3
        struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
        struct ir3_shader_variant *v = ir3_kernel->v;
 
-       const struct ir3_const_state *const_state = &v->shader->const_state;
+       const struct ir3_const_state *const_state = ir3_const_state(v);
        uint32_t base = const_state->offsets.immediate;
        int size = const_state->immediates_count;