* missing UBWC blockwidth/blockheight for npot+64 cpp
* missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
*/
-static const struct {
+static const struct tile_alignment {
unsigned basealign;
unsigned pitchalign;
unsigned heightalign;
+ /* UBWC block width/height. Used in size alignment, and calculating a
+ * descriptor's FLAG_BUFFER_LOG2W/H for mipmapping.
+ */
uint8_t ubwc_blockwidth;
uint8_t ubwc_blockheight;
} tile_alignment[] = {
[64] = { 256, 64, 16 },
/* special cases for r8g8: */
- [0] = { 256, 64, 32, 16, 4 },
+ [0] = { 256, 64, 32, 16, 8 },
};
#define RGB_TILE_WIDTH_ALIGNMENT 64
#define RGB_TILE_HEIGHT_ALIGNMENT 16
#define UBWC_PLANE_SIZE_ALIGNMENT 4096
-static int
-fdl6_pitchalign(struct fdl_layout *layout, int ta, int level)
+static const struct tile_alignment *
+fdl6_tile_alignment(struct fdl_layout *layout)
{
- const struct util_format_description *format_desc =
- util_format_description(layout->format);
+ debug_assert(layout->cpp < ARRAY_SIZE(tile_alignment));
+
+ if ((layout->cpp == 2) && (util_format_get_nr_components(layout->format) == 2))
+ return &tile_alignment[0];
+ else
+ return &tile_alignment[layout->cpp];
+}
+static int
+fdl6_pitchalign(struct fdl_layout *layout, int level)
+{
uint32_t pitchalign = 64;
if (fdl_tile_mode(layout, level))
- pitchalign = tile_alignment[ta].pitchalign;
- if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC)
- pitchalign *= util_format_get_blockwidth(layout->format);
+ pitchalign = fdl6_tile_alignment(layout)->pitchalign;
+
return pitchalign;
}
if (tile_alignment[layout->cpp].ubwc_blockwidth == 0)
layout->ubwc = false;
- int ta = layout->cpp;
-
- /* The z16/r16 formats seem to not play by the normal tiling rules: */
- if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
- ta = 0;
+ const struct tile_alignment *ta = fdl6_tile_alignment(layout);
/* in layer_first layout, the level (slice) contains just one
* layer (since in fact the layer contains the slices)
*/
uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
- debug_assert(ta < ARRAY_SIZE(tile_alignment));
- debug_assert(tile_alignment[ta].pitchalign);
+ debug_assert(ta->pitchalign);
if (layout->tile_mode) {
- layout->base_align = tile_alignment[ta].basealign;
+ layout->base_align = ta->basealign;
} else {
layout->base_align = 64;
}
- uint32_t pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, ta, 0));
+ uint32_t pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, 0));
+
+ uint32_t ubwc_width0 = width0;
+ uint32_t ubwc_height0 = height0;
+ if (mip_levels > 1) {
+ /* With mipmapping enabled, UBWC layout is power-of-two sized,
+ * specified in log2 width/height in the descriptors.
+ */
+ ubwc_width0 = util_next_power_of_two(width0);
+ ubwc_height0 = util_next_power_of_two(height0);
+ }
+ ubwc_width0 = align(DIV_ROUND_UP(ubwc_width0, ta->ubwc_blockwidth),
+ RGB_TILE_WIDTH_ALIGNMENT);
+ ubwc_height0 = align(DIV_ROUND_UP(ubwc_height0, ta->ubwc_blockheight),
+ RGB_TILE_HEIGHT_ALIGNMENT);
for (uint32_t level = 0; level < mip_levels; level++) {
uint32_t depth = u_minify(depth0, level);
struct fdl_slice *slice = &layout->slices[level];
struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
uint32_t tile_mode = fdl_tile_mode(layout, level);
- uint32_t width, height;
+ uint32_t height;
/* tiled levels of 3D textures are rounded up to PoT dimensions: */
if (is_3d && tile_mode) {
- width = u_minify(util_next_power_of_two(width0), level);
height = u_minify(util_next_power_of_two(height0), level);
} else {
- width = u_minify(width0, level);
height = u_minify(height0, level);
}
+ uint32_t nblocksy = util_format_get_nblocksy(format, height);
if (tile_mode)
- height = align(height, tile_alignment[ta].heightalign);
+ nblocksy = align(nblocksy, ta->heightalign);
/* The blits used for mem<->gmem work at a granularity of
* 32x32, which can cause faults due to over-fetch on the
* may not be:
*/
if (level == mip_levels - 1)
- height = align(height, 32);
+ nblocksy = align(nblocksy, 32);
- slice->pitch = util_align_npot(u_minify(pitch0, level),
- fdl6_pitchalign(layout, ta, level));
+ uint32_t nblocksx =
+ util_align_npot(util_format_get_nblocksx(format, u_minify(pitch0, level)),
+ fdl6_pitchalign(layout, level));
slice->offset = layout->size;
- uint32_t blocks = util_format_get_nblocks(format,
- slice->pitch, height);
+ uint32_t blocks = nblocksx * nblocksy;
+
+ slice->pitch = nblocksx * layout->cpp;
/* 1d array and 2d array textures must all have the same layer size
* for each miplevel on a6xx. 3d textures can have different layer
/* with UBWC every level is aligned to 4K */
layout->size = align(layout->size, 4096);
- uint32_t block_width = tile_alignment[ta].ubwc_blockwidth;
- uint32_t block_height = tile_alignment[ta].ubwc_blockheight;
- uint32_t meta_pitch = align(DIV_ROUND_UP(width, block_width),
+ uint32_t meta_pitch = align(u_minify(ubwc_width0, level),
RGB_TILE_WIDTH_ALIGNMENT);
- uint32_t meta_height = align(DIV_ROUND_UP(height, block_height),
+ uint32_t meta_height = align(u_minify(ubwc_height0, level),
RGB_TILE_HEIGHT_ALIGNMENT);
- /* it looks like mipmaps need alignment to power of two
- * TODO: needs testing with large npot textures
- * (needed for the first level?)
- */
- if (mip_levels > 1) {
- meta_pitch = util_next_power_of_two(meta_pitch);
- meta_height = util_next_power_of_two(meta_height);
- }
-
ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
ubwc_slice->pitch = meta_pitch;
ubwc_slice->offset = layout->ubwc_layer_size;
fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
uint32_t *blockwidth, uint32_t *blockheight)
{
- *blockwidth = tile_alignment[layout->cpp].ubwc_blockwidth;
- *blockheight = tile_alignment[layout->cpp].ubwc_blockheight;
+ const struct tile_alignment *ta = fdl6_tile_alignment(layout);
+ *blockwidth = ta->ubwc_blockwidth;
+ *blockheight = ta->ubwc_blockheight;
}
projects / mesa.git / blobdiff