freedreno/a6xx: Fix UBWC mipmap sizing.
[mesa.git] / src / freedreno / fdl / fd6_layout.c
index 82b3a3e715cd285d53f5c70b3b5fbcc9b4e29071..7b544fb7c6fd672e97bdd370bf36f74bf7e0a89c 100644 (file)
 
 #include "freedreno_layout.h"
 
-/* indexed by cpp, including msaa 2x and 4x: */
-static const struct {
+/* indexed by cpp, including msaa 2x and 4x:
+ * TODO:
+ * cpp=1 UBWC needs testing at larger texture sizes
+ * missing UBWC blockwidth/blockheight for npot+64 cpp
+ * missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
+ */
+static const struct tile_alignment {
+       unsigned basealign;
        unsigned pitchalign;
        unsigned heightalign;
+       /* UBWC block width/height.  Used in size alignment, and calculating a
+        * descriptor's FLAG_BUFFER_LOG2W/H for mipmapping.
+        */
+       uint8_t ubwc_blockwidth;
+       uint8_t ubwc_blockheight;
 } tile_alignment[] = {
-       [1]  = { 128, 32 },
-       [2]  = { 128, 16 },
-       [3]  = {  64, 32 },
-       [4]  = {  64, 16 },
-       [6]  = {  64, 16 },
-       [8]  = {  64, 16 },
-       [12] = {  64, 16 },
-       [16] = {  64, 16 },
-       [24] = {  64, 16 },
-       [32] = {  64, 16 },
-       [48] = {  64, 16 },
-       [64] = {  64, 16 },
+       [1]  = {  64, 128, 32, 16, 4 },
+       [2]  = { 128, 128, 16, 16, 4 },
+       [3]  = { 256,  64, 32 },
+       [4]  = { 256,  64, 16, 16, 4 },
+       [6]  = { 256,  64, 16 },
+       [8]  = { 256,  64, 16, 8, 4, },
+       [12] = { 256,  64, 16 },
+       [16] = { 256,  64, 16, 4, 4, },
+       [24] = { 256,  64, 16 },
+       [32] = { 256,  64, 16, 4, 2 },
+       [48] = { 256,  64, 16 },
+       [64] = { 256,  64, 16 },
 
        /* special cases for r8g8: */
-       [0]  = {  64, 32 },
+       [0]  = { 256, 64, 32, 16, 8 },
 };
 
+#define RGB_TILE_WIDTH_ALIGNMENT 64
+#define RGB_TILE_HEIGHT_ALIGNMENT 16
+#define UBWC_PLANE_SIZE_ALIGNMENT 4096
+
+static const struct tile_alignment *
+fdl6_tile_alignment(struct fdl_layout *layout)
+{
+       debug_assert(layout->cpp < ARRAY_SIZE(tile_alignment));
+
+       if ((layout->cpp == 2) && (util_format_get_nr_components(layout->format) == 2))
+               return &tile_alignment[0];
+       else
+               return &tile_alignment[layout->cpp];
+}
+
+static int
+fdl6_pitchalign(struct fdl_layout *layout, int level)
+{
+       uint32_t pitchalign = 64;
+       if (fdl_tile_mode(layout, level))
+               pitchalign = fdl6_tile_alignment(layout)->pitchalign;
+
+       return pitchalign;
+}
+
 /* NOTE: good way to test this is:  (for example)
  *  piglit/bin/texelFetch fs sampler3D 100x100x8
  */
@@ -67,62 +103,65 @@ fdl6_layout(struct fdl_layout *layout,
 
        layout->cpp = util_format_get_blocksize(format);
        layout->cpp *= nr_samples;
+       layout->cpp_shift = ffs(layout->cpp) - 1;
+
+       layout->format = format;
+       layout->nr_samples = nr_samples;
+       layout->layer_first = !is_3d;
+
+       if (depth0 > 1)
+               layout->ubwc = false;
+       if (tile_alignment[layout->cpp].ubwc_blockwidth == 0)
+               layout->ubwc = false;
+
+       const struct tile_alignment *ta = fdl6_tile_alignment(layout);
 
-       const struct util_format_description *format_desc =
-               util_format_description(format);
-       uint32_t level;
-       uint32_t depth = depth0;
-       /* linear dimensions: */
-       uint32_t lwidth = width0;
-       uint32_t lheight = height0;
-       /* tile_mode dimensions: */
-       uint32_t twidth = util_next_power_of_two(lwidth);
-       uint32_t theight = util_next_power_of_two(lheight);
-       int ta = layout->cpp;
-
-       /* The z16/r16 formats seem to not play by the normal tiling rules: */
-       if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
-               ta = 0;
-
-       uint32_t alignment;
-       if (is_3d) {
-               layout->layer_first = false;
-               alignment = 4096;
-       } else {
-               layout->layer_first = true;
-               alignment = 1;
-       }
        /* in layer_first layout, the level (slice) contains just one
         * layer (since in fact the layer contains the slices)
         */
        uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
 
-       debug_assert(ta < ARRAY_SIZE(tile_alignment));
-       debug_assert(tile_alignment[ta].pitchalign);
+       debug_assert(ta->pitchalign);
+
+       if (layout->tile_mode) {
+               layout->base_align = ta->basealign;
+       } else {
+               layout->base_align = 64;
+       }
+
+       uint32_t pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, 0));
+
+       uint32_t ubwc_width0 = width0;
+       uint32_t ubwc_height0 = height0;
+       if (mip_levels > 1) {
+               /* With mipmapping enabled, UBWC layout is power-of-two sized,
+                * specified in log2 width/height in the descriptors.
+                */
+               ubwc_width0 = util_next_power_of_two(width0);
+               ubwc_height0 = util_next_power_of_two(height0);
+       }
+       ubwc_width0 = align(DIV_ROUND_UP(ubwc_width0, ta->ubwc_blockwidth),
+                       RGB_TILE_WIDTH_ALIGNMENT);
+       ubwc_height0 = align(DIV_ROUND_UP(ubwc_height0, ta->ubwc_blockheight),
+                       RGB_TILE_HEIGHT_ALIGNMENT);
 
-       for (level = 0; level < mip_levels; level++) {
+       for (uint32_t level = 0; level < mip_levels; level++) {
+               uint32_t depth = u_minify(depth0, level);
                struct fdl_slice *slice = &layout->slices[level];
+               struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
                uint32_t tile_mode = fdl_tile_mode(layout, level);
-               uint32_t width, height;
+               uint32_t height;
 
                /* tiled levels of 3D textures are rounded up to PoT dimensions: */
                if (is_3d && tile_mode) {
-                       width = twidth;
-                       height = theight;
+                       height = u_minify(util_next_power_of_two(height0), level);
                } else {
-                       width = lwidth;
-                       height = lheight;
+                       height = u_minify(height0, level);
                }
-               uint32_t aligned_height = height;
-               uint32_t pitchalign;
 
-               if (tile_mode) {
-                       pitchalign = tile_alignment[ta].pitchalign;
-                       aligned_height = align(aligned_height,
-                                       tile_alignment[ta].heightalign);
-               } else {
-                       pitchalign = 64;
-               }
+               uint32_t nblocksy = util_format_get_nblocksy(format, height);
+               if (tile_mode)
+                       nblocksy = align(nblocksy, ta->heightalign);
 
                /* The blits used for mem<->gmem work at a granularity of
                 * 32x32, which can cause faults due to over-fetch on the
@@ -132,17 +171,16 @@ fdl6_layout(struct fdl_layout *layout,
                 * may not be:
                 */
                if (level == mip_levels - 1)
-                       aligned_height = align(aligned_height, 32);
+                       nblocksy = align(nblocksy, 32);
 
-               if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC)
-                       slice->pitch =
-                               util_align_npot(width, pitchalign * util_format_get_blockwidth(format));
-               else
-                       slice->pitch = align(width, pitchalign);
+               uint32_t nblocksx =
+                       util_align_npot(util_format_get_nblocksx(format, u_minify(pitch0, level)),
+                                       fdl6_pitchalign(layout, level));
 
                slice->offset = layout->size;
-               uint32_t blocks = util_format_get_nblocks(format,
-                               slice->pitch, aligned_height);
+               uint32_t blocks = nblocksx * nblocksy;
+
+               slice->pitch = nblocksx * layout->cpp;
 
                /* 1d array and 2d array textures must all have the same layer size
                 * for each miplevel on a6xx. 3d textures can have different layer
@@ -152,34 +190,54 @@ fdl6_layout(struct fdl_layout *layout,
                 */
                if (is_3d) {
                        if (level < 1 || layout->slices[level - 1].size0 > 0xf000) {
-                               slice->size0 = align(blocks * layout->cpp, alignment);
+                               slice->size0 = align(blocks * layout->cpp, 4096);
                        } else {
                                slice->size0 = layout->slices[level - 1].size0;
                        }
                } else {
-                       slice->size0 = align(blocks * layout->cpp, alignment);
+                       slice->size0 = blocks * layout->cpp;
                }
 
                layout->size += slice->size0 * depth * layers_in_level;
 
-               if (false) {
-                       fprintf(stderr, "%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u, offset=0x%x tiling=%d\n",
-                                       util_format_name(format),
-                                       width, height, depth, layout->cpp,
-                                       level, slice->pitch * layout->cpp,
-                                       slice->size0, layout->size, aligned_height, blocks,
-                                       slice->offset, tile_mode);
-               }
+               if (layout->ubwc) {
+                       /* with UBWC every level is aligned to 4K */
+                       layout->size = align(layout->size, 4096);
 
-               depth = u_minify(depth, 1);
-               lwidth = u_minify(lwidth, 1);
-               lheight = u_minify(lheight, 1);
-               twidth = u_minify(twidth, 1);
-               theight = u_minify(theight, 1);
+                       uint32_t meta_pitch = align(u_minify(ubwc_width0, level),
+                                       RGB_TILE_WIDTH_ALIGNMENT);
+                       uint32_t meta_height = align(u_minify(ubwc_height0, level),
+                                       RGB_TILE_HEIGHT_ALIGNMENT);
+
+                       ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
+                       ubwc_slice->pitch = meta_pitch;
+                       ubwc_slice->offset = layout->ubwc_layer_size;
+                       layout->ubwc_layer_size += ubwc_slice->size0;
+               }
        }
 
        if (layout->layer_first) {
                layout->layer_size = align(layout->size, 4096);
                layout->size = layout->layer_size * array_size;
        }
+
+       /* Place the UBWC slices before the uncompressed slices, because the
+        * kernel expects UBWC to be at the start of the buffer.  In the HW, we
+        * get to program the UBWC and non-UBWC offset/strides
+        * independently.
+        */
+       if (layout->ubwc) {
+               for (uint32_t level = 0; level < mip_levels; level++)
+                       layout->slices[level].offset += layout->ubwc_layer_size * array_size;
+               layout->size += layout->ubwc_layer_size * array_size;
+       }
+}
+
+void
+fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
+               uint32_t *blockwidth, uint32_t *blockheight)
+{
+       const struct tile_alignment *ta = fdl6_tile_alignment(layout);
+       *blockwidth = ta->ubwc_blockwidth;
+       *blockheight = ta->ubwc_blockheight;
 }