freedreno/a6xx: Fix UBWC mipmap sizing.

[mesa.git] / src / freedreno / fdl / fd6_layout.c

diff --git a/src/freedreno/fdl/fd6_layout.c b/src/freedreno/fdl/fd6_layout.c
index d6a83bfdd4a9f09596b58109efe3051e02fbaecd..7b544fb7c6fd672e97bdd370bf36f74bf7e0a89c 100644 (file)
--- a/src/freedreno/fdl/fd6_layout.c
+++ b/src/freedreno/fdl/fd6_layout.c
@@ -39,6 +39,9 @@ static const struct tile_alignment {
        unsigned basealign;
        unsigned pitchalign;
        unsigned heightalign;
+       /* UBWC block width/height.  Used in size alignment, and calculating a
+        * descriptor's FLAG_BUFFER_LOG2W/H for mipmapping.
+        */
        uint8_t ubwc_blockwidth;
        uint8_t ubwc_blockheight;
 } tile_alignment[] = {
@@ -56,7 +59,7 @@ static const struct tile_alignment {
        [64] = { 256,  64, 16 },
 
        /* special cases for r8g8: */
-       [0]  = { 256, 64, 32, 16, 4 },
+       [0]  = { 256, 64, 32, 16, 8 },
 };
 
 #define RGB_TILE_WIDTH_ALIGNMENT 64
@@ -128,19 +131,31 @@ fdl6_layout(struct fdl_layout *layout,
 
        uint32_t pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, 0));
 
+       uint32_t ubwc_width0 = width0;
+       uint32_t ubwc_height0 = height0;
+       if (mip_levels > 1) {
+               /* With mipmapping enabled, UBWC layout is power-of-two sized,
+                * specified in log2 width/height in the descriptors.
+                */
+               ubwc_width0 = util_next_power_of_two(width0);
+               ubwc_height0 = util_next_power_of_two(height0);
+       }
+       ubwc_width0 = align(DIV_ROUND_UP(ubwc_width0, ta->ubwc_blockwidth),
+                       RGB_TILE_WIDTH_ALIGNMENT);
+       ubwc_height0 = align(DIV_ROUND_UP(ubwc_height0, ta->ubwc_blockheight),
+                       RGB_TILE_HEIGHT_ALIGNMENT);
+
        for (uint32_t level = 0; level < mip_levels; level++) {
                uint32_t depth = u_minify(depth0, level);
                struct fdl_slice *slice = &layout->slices[level];
                struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
                uint32_t tile_mode = fdl_tile_mode(layout, level);
-               uint32_t width, height;
+               uint32_t height;
 
                /* tiled levels of 3D textures are rounded up to PoT dimensions: */
                if (is_3d && tile_mode) {
-                       width = u_minify(util_next_power_of_two(width0), level);
                        height = u_minify(util_next_power_of_two(height0), level);
                } else {
-                       width = u_minify(width0, level);
                        height = u_minify(height0, level);
                }
 
@@ -189,20 +204,11 @@ fdl6_layout(struct fdl_layout *layout,
                        /* with UBWC every level is aligned to 4K */
                        layout->size = align(layout->size, 4096);
 
-                       uint32_t meta_pitch = align(DIV_ROUND_UP(width, ta->ubwc_blockwidth),
+                       uint32_t meta_pitch = align(u_minify(ubwc_width0, level),
                                        RGB_TILE_WIDTH_ALIGNMENT);
-                       uint32_t meta_height = align(DIV_ROUND_UP(height, ta->ubwc_blockheight),
+                       uint32_t meta_height = align(u_minify(ubwc_height0, level),
                                        RGB_TILE_HEIGHT_ALIGNMENT);
 
-                       /* it looks like mipmaps need alignment to power of two
-                        * TODO: needs testing with large npot textures
-                        * (needed for the first level?)
-                        */
-                       if (mip_levels > 1) {
-                               meta_pitch = util_next_power_of_two(meta_pitch);
-                               meta_height = util_next_power_of_two(meta_height);
-                       }
-
                        ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
                        ubwc_slice->pitch = meta_pitch;
                        ubwc_slice->offset = layout->ubwc_layer_size;