void
ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
{
- NIR_PASS_V(s, nir_lower_io, nir_var_all, ir3_glsl_type_size,
- (nir_lower_io_options)0);
+ NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
+ ir3_glsl_type_size, (nir_lower_io_options)0);
if (s->info.stage == MESA_SHADER_FRAGMENT) {
/* NOTE: lower load_barycentric_at_sample first, since it
MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
break;
case nir_intrinsic_load_user_clip_plane:
+ idx = nir_intrinsic_ucp_id(intr);
layout->num_driver_params =
- MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
+ MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
break;
case nir_intrinsic_load_num_work_groups:
layout->num_driver_params =