ir3: use empirical size for params as used by the shader

[mesa.git] / src / freedreno / ir3 / ir3_nir.c

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index bf2db6b6c9cb470a593dc0308b4e23234c604fa4..196c99f302435741837dcd08db5d41bc37fc1e81 100644 (file)
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -215,14 +215,14 @@ should_split_wrmask(const nir_instr *instr, const void *data)
 }
 
 void
-ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
+ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
 {
        struct nir_lower_tex_options tex_options = {
                        .lower_rect = 0,
                        .lower_tg4_offsets = true,
        };
 
-       if (shader->compiler->gpu_id >= 400) {
+       if (compiler->gpu_id >= 400) {
                /* a4xx seems to have *no* sam.p */
                tex_options.lower_txp = ~0;  /* lower all txp */
        } else {
@@ -236,17 +236,19 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
                debug_printf("----------------------\n");
        }
 
-       OPT_V(s, nir_lower_regs_to_ssa);
-       OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
+       if (s->info.stage == MESA_SHADER_GEOMETRY)
+               NIR_PASS_V(s, ir3_nir_lower_gs);
 
-       OPT_V(s, ir3_nir_apply_trig_workarounds);
+       NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
 
-       if (shader->type == MESA_SHADER_FRAGMENT)
-               OPT_V(s, nir_lower_fb_read);
+       NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
+
+       OPT_V(s, nir_lower_regs_to_ssa);
+       OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
 
        OPT_V(s, nir_lower_tex, &tex_options);
        OPT_V(s, nir_lower_load_const_to_scalar);
-       if (shader->compiler->gpu_id < 500)
+       if (compiler->gpu_id < 500)
                OPT_V(s, ir3_nir_lower_tg4_to_tex);
 
        ir3_optimize_loop(s);
@@ -270,6 +272,39 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
        nir_sweep(s);
 }
 
+/**
+ * Late passes that need to be done after pscreen->finalize_nir()
+ */
+void
+ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
+{
+       NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
+                          ir3_glsl_type_size, (nir_lower_io_options)0);
+
+       if (s->info.stage == MESA_SHADER_FRAGMENT) {
+               /* NOTE: lower load_barycentric_at_sample first, since it
+                * produces load_barycentric_at_offset:
+                */
+               NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
+               NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
+               NIR_PASS_V(s, ir3_nir_move_varying_inputs);
+               NIR_PASS_V(s, nir_lower_fb_read);
+       }
+
+       if (compiler->gpu_id >= 600 &&
+                       s->info.stage == MESA_SHADER_FRAGMENT &&
+                       !(ir3_shader_debug & IR3_DBG_NOFP16)) {
+               NIR_PASS_V(s, nir_lower_mediump_outputs);
+       }
+
+       /* we cannot ensure that ir3_finalize_nir() is only called once, so
+        * we also need to do trig workarounds here:
+        */
+       OPT_V(s, ir3_nir_apply_trig_workarounds);
+
+       ir3_optimize_loop(s);
+}
+
 void
 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
 {
@@ -448,8 +483,9 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
                                                MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
                                        break;
                                case nir_intrinsic_load_user_clip_plane:
+                                       idx = nir_intrinsic_ucp_id(intr);
                                        layout->num_driver_params =
-                                               MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
+                                               MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
                                        break;
                                case nir_intrinsic_load_num_work_groups:
                                        layout->num_driver_params =