.lower_helper_invocation = true,
.lower_bitfield_insert_to_shifts = true,
.lower_bitfield_extract_to_shifts = true,
- .lower_bfm = true,
.use_interpolated_input_intrinsics = true,
+ .lower_rotate = true,
+ .lower_to_scalar = true,
};
/* we don't want to lower vertex_id to _zero_based on newer gpus: */
.lower_helper_invocation = true,
.lower_bitfield_insert_to_shifts = true,
.lower_bitfield_extract_to_shifts = true,
- .lower_bfm = true,
.use_interpolated_input_intrinsics = true,
+ .lower_rotate = true,
+ .vectorize_io = true,
+ .lower_to_scalar = true,
};
const nir_shader_compiler_options *
OPT_V(s, nir_lower_vars_to_ssa);
progress |= OPT(s, nir_opt_copy_prop_vars);
progress |= OPT(s, nir_opt_dead_write_vars);
- progress |= OPT(s, nir_lower_alu_to_scalar, NULL);
+ progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
progress |= OPT(s, nir_lower_phis_to_scalar);
progress |= OPT(s, nir_copy_prop);
} while (progress);
}
-struct nir_shader *
+void
ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
const struct ir3_shader_key *key)
{
if (key) {
if (s->info.stage == MESA_SHADER_VERTEX) {
- OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
+ OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false, false);
if (key->vclamp_color)
OPT_V(s, nir_lower_clamp_color_outputs);
} else if (s->info.stage == MESA_SHADER_FRAGMENT) {
- OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
+ OPT_V(s, nir_lower_clip_fs, key->ucp_enables, false);
if (key->fclamp_color)
OPT_V(s, nir_lower_clamp_color_outputs);
}
if (ubo_progress || idiv_progress)
ir3_optimize_loop(s);
+ /* Do late algebraic optimization to turn add(a, neg(b)) back into
+ * subs, then the mandatory cleanup after algebraic. Note that it may
+ * produce fnegs, and if so then we need to keep running to squash
+ * fneg(fneg(a)).
+ */
+ bool more_late_algebraic = true;
+ while (more_late_algebraic) {
+ more_late_algebraic = OPT(s, nir_opt_algebraic_late);
+ OPT_V(s, nir_opt_constant_folding);
+ OPT_V(s, nir_copy_prop);
+ OPT_V(s, nir_opt_dce);
+ OPT_V(s, nir_opt_cse);
+ }
+
OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
- OPT_V(s, nir_move_load_const);
+ OPT_V(s, nir_opt_sink, nir_move_const_undef);
if (ir3_shader_debug & IR3_DBG_DISASM) {
debug_printf("----------------------\n");
if (!key) {
ir3_setup_const_state(shader, s);
}
-
- return s;
}
static void
layout->ssbo_size.count += 1; /* one const per */
break;
case nir_intrinsic_image_deref_atomic_add:
- case nir_intrinsic_image_deref_atomic_min:
- case nir_intrinsic_image_deref_atomic_max:
+ case nir_intrinsic_image_deref_atomic_imin:
+ case nir_intrinsic_image_deref_atomic_umin:
+ case nir_intrinsic_image_deref_atomic_imax:
+ case nir_intrinsic_image_deref_atomic_umax:
case nir_intrinsic_image_deref_atomic_and:
case nir_intrinsic_image_deref_atomic_or:
case nir_intrinsic_image_deref_atomic_xor:
layout->image_dims.count;
layout->image_dims.count += 3; /* three const per */
break;
+ case nir_intrinsic_load_ubo:
+ if (nir_src_is_const(intr->src[0])) {
+ layout->num_ubos = MAX2(layout->num_ubos,
+ nir_src_as_uint(intr->src[0]) + 1);
+ } else {
+ layout->num_ubos = shader->info.num_ubos;
+ }
+ break;
+ case nir_intrinsic_load_base_vertex:
+ case nir_intrinsic_load_first_vertex:
+ layout->num_driver_params =
+ MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
+ break;
+ case nir_intrinsic_load_user_clip_plane:
+ layout->num_driver_params =
+ MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
+ break;
+ case nir_intrinsic_load_num_work_groups:
+ layout->num_driver_params =
+ MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
+ break;
+ case nir_intrinsic_load_local_group_size:
+ layout->num_driver_params =
+ MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
+ break;
default:
break;
}
ir3_nir_scan_driver_consts(nir, const_state);
- const_state->num_uniforms = nir->num_uniforms;
- const_state->num_ubos = nir->info.num_ubos;
+ if ((compiler->gpu_id < 500) &&
+ (shader->stream_output.num_outputs > 0)) {
+ const_state->num_driver_params =
+ MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
+ }
+
+ /* num_driver_params is scalar, align to vec4: */
+ const_state->num_driver_params = align(const_state->num_driver_params, 4);
debug_assert((shader->ubo_state.size % 16) == 0);
- unsigned constoff = align(shader->ubo_state.size / 16, 4);
+ unsigned constoff = align(shader->ubo_state.size / 16, 8);
unsigned ptrsz = ir3_pointer_size(compiler);
if (const_state->num_ubos > 0) {
constoff += align(cnt, 4) / 4;
}
- unsigned num_driver_params = 0;
- if (shader->type == MESA_SHADER_VERTEX) {
- num_driver_params = IR3_DP_VS_COUNT;
- } else if (shader->type == MESA_SHADER_COMPUTE) {
- num_driver_params = IR3_DP_CS_COUNT;
- }
-
- const_state->offsets.driver_param = constoff;
- constoff += align(num_driver_params, 4) / 4;
+ if (const_state->num_driver_params > 0)
+ const_state->offsets.driver_param = constoff;
+ constoff += const_state->num_driver_params / 4;
if ((shader->type == MESA_SHADER_VERTEX) &&
(compiler->gpu_id < 500) &&
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