#include "util/bitset.h"
#include "ir3.h"
-#include "ir3_compiler.h"
+#include "ir3_shader.h"
#include "ir3_ra.h"
return !((a_start >= b_end) || (b_start >= a_end));
}
-static unsigned
-reg_size_for_array(struct ir3_array *arr)
-{
- if (arr->half)
- return DIV_ROUND_UP(arr->length, 2);
-
- return arr->length;
-}
-
static bool
instr_before(struct ir3_instruction *a, struct ir3_instruction *b)
{
* need to find the distance between where actual array starts
* and collect.. that probably doesn't happen currently.
*/
- struct ir3_register *src;
int dsz, doff;
/* note: don't use foreach_ssa_src as this gets called once
dd = get_definer(ctx, d->regs[1]->instr, &dsz, &doff);
/* by definition, should come before: */
- debug_assert(instr_before(dd, d));
+ ra_assert(ctx, instr_before(dd, d));
*sz = MAX2(*sz, dsz);
d = dd;
}
- debug_assert(d->opc != OPC_META_SPLIT);
+ ra_assert(ctx, d->opc != OPC_META_SPLIT);
id->defn = d;
id->sz = *sz;
return pick_in_range(regs, base, base + max_target);
}
} else {
- assert(sz == 1);
+ ra_assert(ctx, sz == 1);
}
/* NOTE: this is only used in scalar pass, so the register
* for write after read hazards:
*/
struct ir3_instruction *instr = name_to_instr(ctx, n);
- if (is_sfu(instr) && instr->regs[1]->instr) {
- struct ir3_instruction *src = instr->regs[1]->instr;
- unsigned src_n = scalar_name(ctx, src, 0);
+ if (is_sfu(instr)) {
+ struct ir3_register *src = instr->regs[1];
+ int src_n;
+
+ if ((src->flags & IR3_REG_ARRAY) && !(src->flags & IR3_REG_RELATIV)) {
+ struct ir3_array *arr = ir3_lookup_array(ctx->ir, src->array.id);
+ src_n = arr->base + src->array.offset;
+ } else {
+ src_n = scalar_name(ctx, src->instr, 0);
+ }
unsigned reg = ra_get_node_reg(ctx->g, src_n);
return reg;
}
}
- } else if (is_tex_or_prefetch(instr)) {
- /* we could have a tex fetch w/ wrmask .z, for example.. these
- * cannot land in r0.x since that would underflow when we
- * subtract the offset. Ie. if we pick r0.z, and subtract
- * the offset, the register encoded for dst will be r0.x
- */
- unsigned n = ffs(instr->regs[0]->wrmask);
- debug_assert(n > 0);
- unsigned offset = n - 1;
- if (!half)
- offset *= 2;
- base += offset;
- max_target -= offset;
}
int r = pick_in_range(regs, base + start, base + max_target);
unsigned n, base;
ir3_clear_mark(ctx->ir);
- n = ir3_count_instructions(ctx->ir);
+ n = ir3_count_instructions_ra(ctx->ir);
ctx->instrd = rzalloc_array(NULL, struct ir3_ra_instr_data, n);
base = ctx->class_base[total_class_count];
foreach_array (arr, &ctx->ir->array_list) {
arr->base = base;
- ctx->class_alloc_count[total_class_count] += reg_size_for_array(arr);
- base += reg_size_for_array(arr);
+ ctx->class_alloc_count[total_class_count] += arr->length;
+ base += arr->length;
}
ctx->alloc_count += ctx->class_alloc_count[total_class_count];
+ /* Add vreg names for r0.xyz */
+ ctx->r0_xyz_nodes = ctx->alloc_count;
+ ctx->alloc_count += 3;
+ ctx->hr0_xyz_nodes = ctx->alloc_count;
+ ctx->alloc_count += 3;
+
+ /* Add vreg name for prefetch-exclusion range: */
+ ctx->prefetch_exclude_node = ctx->alloc_count++;
+
+ if (RA_DEBUG) {
+ d("INSTRUCTION VREG NAMES:");
+ foreach_block (block, &ctx->ir->block_list) {
+ foreach_instr (instr, &block->instr_list) {
+ if (!ctx->instrd[instr->ip].defn)
+ continue;
+ if (!writes_gpr(instr))
+ continue;
+ di(instr, "%04u", scalar_name(ctx, instr, 0));
+ }
+ }
+ d("ARRAY VREG NAMES:");
+ foreach_array (arr, &ctx->ir->array_list) {
+ d("%04u: arr%u", arr->base, arr->id);
+ }
+ d("EXTRA VREG NAMES:");
+ d("%04u: r0_xyz_nodes", ctx->r0_xyz_nodes);
+ d("%04u: hr0_xyz_nodes", ctx->hr0_xyz_nodes);
+ d("%04u: prefetch_exclude_node", ctx->prefetch_exclude_node);
+ }
+
ctx->g = ra_alloc_interference_graph(ctx->set->regs, ctx->alloc_count);
ralloc_steal(ctx->g, ctx->instrd);
ctx->def = rzalloc_array(ctx->g, unsigned, ctx->alloc_count);
ctx->use = rzalloc_array(ctx->g, unsigned, ctx->alloc_count);
/* TODO add selector callback for split (pre-a6xx) register file: */
- if (ctx->ir->compiler->gpu_id >= 600) {
+ if (ctx->v->mergedregs) {
ra_set_select_reg_callback(ctx->g, ra_select_reg_merged, ctx);
if (ctx->scalar_pass) {
static struct ir3_instruction *
name_to_instr(struct ir3_ra_ctx *ctx, unsigned name)
{
- assert(!name_is_array(ctx, name));
+ ra_assert(ctx, !name_is_array(ctx, name));
struct hash_entry *entry = _mesa_hash_table_search(ctx->name_to_instr, &name);
if (entry)
return entry->data;
- unreachable("invalid instr name");
+ ra_unreachable(ctx, "invalid instr name");
return NULL;
}
static struct ir3_array *
name_to_array(struct ir3_ra_ctx *ctx, unsigned name)
{
- assert(name_is_array(ctx, name));
+ ra_assert(ctx, name_is_array(ctx, name));
foreach_array (arr, &ctx->ir->array_list) {
- unsigned sz = reg_size_for_array(arr);
- if (name < (arr->base + sz))
+ if (name < (arr->base + arr->length))
return arr;
}
- unreachable("invalid array name");
+ ra_unreachable(ctx, "invalid array name");
return NULL;
}
__def(struct ir3_ra_ctx *ctx, struct ir3_ra_block_data *bd, unsigned name,
struct ir3_instruction *instr)
{
- debug_assert(name < ctx->alloc_count);
+ ra_assert(ctx, name < ctx->alloc_count);
/* split/collect do not actually define any real value */
if ((instr->opc == OPC_META_SPLIT) || (instr->opc == OPC_META_COLLECT))
__use(struct ir3_ra_ctx *ctx, struct ir3_ra_block_data *bd, unsigned name,
struct ir3_instruction *instr)
{
- debug_assert(name < ctx->alloc_count);
+ ra_assert(ctx, name < ctx->alloc_count);
ctx->use[name] = MAX2(ctx->use[name], instr->ip);
if (!BITSET_TEST(bd->def, name))
BITSET_SET(bd->use, name);
if ((instr->opc == OPC_META_INPUT) && first_non_input)
use(name, first_non_input);
+
+ /* Texture instructions with writemasks can be treated as smaller
+ * vectors (or just scalars!) to allocate knowing that the
+ * masked-out regs won't be written, but we need to make sure that
+ * the start of the vector doesn't come before the first register
+ * or we'll wrap.
+ */
+ if (is_tex_or_prefetch(instr)) {
+ int writemask_skipped_regs = ffs(instr->regs[0]->wrmask) - 1;
+ int r0_xyz = is_half(instr) ?
+ ctx->hr0_xyz_nodes : ctx->r0_xyz_nodes;
+ for (int i = 0; i < writemask_skipped_regs; i++)
+ ra_add_node_interference(ctx->g, name, r0_xyz + i);
+ }
+
+ /* Pre-fetched textures have a lower limit for bits to encode dst
+ * register, so add additional interference with registers above
+ * that limit.
+ */
+ if (instr->opc == OPC_META_TEX_PREFETCH) {
+ ra_add_node_interference(ctx->g, name,
+ ctx->prefetch_exclude_node);
+ }
}
foreach_use (name, ctx, instr) {
*/
unsigned *key = ralloc(ctx->name_to_instr, unsigned);
*key = name;
- debug_assert(!_mesa_hash_table_search(ctx->name_to_instr, key));
+ ra_assert(ctx, !_mesa_hash_table_search(ctx->name_to_instr, key));
_mesa_hash_table_insert(ctx->name_to_instr, key, instr);
}
}
struct ir3_ra_block_data *bd = block->data;
unsigned name;
- assert(ctx->name_to_instr);
+ ra_assert(ctx, ctx->name_to_instr);
/* TODO this gets a bit more complicated in non-scalar pass.. but
* possibly a lowball estimate is fine to start with if we do
* round-robin in non-scalar pass? Maybe we just want to handle
* that in a different fxn?
*/
- assert(ctx->scalar_pass);
+ ra_assert(ctx, ctx->scalar_pass);
BITSET_WORD *live =
rzalloc_array(bd, BITSET_WORD, BITSET_WORDS(ctx->alloc_count));
cur_live += new_live;
cur_live -= new_dead;
- assert(cur_live >= 0);
+ ra_assert(ctx, cur_live >= 0);
d("CUR_LIVE: %u", cur_live);
max = MAX2(max, cur_live);
* live)
*/
cur_live -= next_dead;
- assert(cur_live >= 0);
+ ra_assert(ctx, cur_live >= 0);
if (RA_DEBUG) {
unsigned cnt = 0;
BITSET_FOREACH_SET (name, live, ctx->alloc_count) {
cnt += name_size(ctx, name);
}
- assert(cur_live == cnt);
+ ra_assert(ctx, cur_live == cnt);
}
}
/* the remaining live should match liveout (for extra sanity testing): */
if (RA_DEBUG) {
+ unsigned new_dead = 0;
+ BITSET_FOREACH_SET (name, live, ctx->alloc_count) {
+ /* Is this the last use? */
+ if (ctx->use[name] != block->end_ip)
+ continue;
+ new_dead += name_size(ctx, name);
+ d("NEW_DEAD: %u (new_dead=%u)", name, new_dead);
+ BITSET_CLEAR(live, name);
+ }
unsigned liveout = 0;
BITSET_FOREACH_SET (name, bd->liveout, ctx->alloc_count) {
liveout += name_size(ctx, name);
* tells us a value is livein. But not used by the block or
* liveout for the block. Possibly a bug in the liverange
* extension. But for now leave the assert disabled:
- assert(cur_live == liveout);
+ ra_assert(ctx, cur_live == liveout);
*/
}
}
arr->end_ip = 0;
}
+ /* set up the r0.xyz precolor regs. */
+ for (int i = 0; i < 3; i++) {
+ ra_set_node_reg(ctx->g, ctx->r0_xyz_nodes + i, i);
+ ra_set_node_reg(ctx->g, ctx->hr0_xyz_nodes + i,
+ ctx->set->first_half_reg + i);
+ }
+
+ /* pre-color node that conflict with half/full regs higher than what
+ * can be encoded for tex-prefetch:
+ */
+ ra_set_node_reg(ctx->g, ctx->prefetch_exclude_node,
+ ctx->set->prefetch_exclude_reg);
+
/* compute live ranges (use/def) on a block level, also updating
* block's def/use bitmasks (used below to calculate per-block
* livein/liveout):
d(" start_ip: %u", arr->start_ip);
d(" end_ip: %u", arr->end_ip);
}
- d("INSTRUCTION VREG NAMES:");
- foreach_block (block, &ctx->ir->block_list) {
- foreach_instr (instr, &block->instr_list) {
- if (!ctx->instrd[instr->ip].defn)
- continue;
- if (!writes_gpr(instr))
- continue;
- di(instr, "%04u", scalar_name(ctx, instr, 0));
- }
- }
- d("ARRAY VREG NAMES:");
- foreach_array (arr, &ctx->ir->array_list) {
- d("%04u: arr%u", arr->base, arr->id);
- }
}
/* extend start/end ranges based on livein/liveout info from cfg: */
}
}
-/* some instructions need fix-up if dst register is half precision: */
-static void fixup_half_instr_dst(struct ir3_instruction *instr)
-{
- switch (opc_cat(instr->opc)) {
- case 1: /* move instructions */
- instr->cat1.dst_type = half_type(instr->cat1.dst_type);
- break;
- case 4:
- switch (instr->opc) {
- case OPC_RSQ:
- instr->opc = OPC_HRSQ;
- break;
- case OPC_LOG2:
- instr->opc = OPC_HLOG2;
- break;
- case OPC_EXP2:
- instr->opc = OPC_HEXP2;
- break;
- default:
- break;
- }
- break;
- case 5:
- instr->cat5.type = half_type(instr->cat5.type);
- break;
- }
-}
-/* some instructions need fix-up if src register is half precision: */
-static void fixup_half_instr_src(struct ir3_instruction *instr)
-{
- switch (instr->opc) {
- case OPC_MOV:
- instr->cat1.src_type = half_type(instr->cat1.src_type);
- break;
- case OPC_MAD_F32:
- instr->opc = OPC_MAD_F16;
- break;
- case OPC_SEL_B32:
- instr->opc = OPC_SEL_B16;
- break;
- case OPC_SEL_S32:
- instr->opc = OPC_SEL_S16;
- break;
- case OPC_SEL_F32:
- instr->opc = OPC_SEL_F16;
- break;
- case OPC_SAD_S32:
- instr->opc = OPC_SAD_S16;
- break;
- default:
- break;
- }
-}
-
/* NOTE: instr could be NULL for IR3_REG_ARRAY case, for the first
* array access(es) which do not have any previous access to depend
* on from scheduling point of view
*/
if (ctx->scalar_pass && is_tex_or_prefetch(id->defn)) {
unsigned n = ffs(id->defn->regs[0]->wrmask);
- debug_assert(n > 0);
+ ra_assert(ctx, n > 0);
first_component = n - 1;
}
unsigned r = ra_get_node_reg(ctx->g, name);
unsigned num = ctx->set->ra_reg_to_gpr[r] + id->off;
- debug_assert(!(reg->flags & IR3_REG_RELATIV));
+ ra_assert(ctx, !(reg->flags & IR3_REG_RELATIV));
- debug_assert(num >= first_component);
+ ra_assert(ctx, num >= first_component);
if (is_high(id->defn))
num += FIRST_HIGH_REG;
ra_block_alloc(struct ir3_ra_ctx *ctx, struct ir3_block *block)
{
foreach_instr (instr, &block->instr_list) {
- struct ir3_register *reg;
if (writes_gpr(instr)) {
if (should_assign(ctx, instr)) {
reg_assign(ctx, instr->regs[0], instr);
- if (instr->regs[0]->flags & IR3_REG_HALF)
- fixup_half_instr_dst(instr);
}
}
/* Note: reg->instr could be null for IR3_REG_ARRAY */
if (src || (reg->flags & IR3_REG_ARRAY))
reg_assign(ctx, instr->regs[n+1], src);
-
- if (instr->regs[n+1]->flags & IR3_REG_HALF)
- fixup_half_instr_src(instr);
}
}
* them in the first pass:
*/
if (!ctx->scalar_pass) {
- struct ir3_instruction *in, *out;
-
foreach_input (in, ctx->ir) {
reg_assign(ctx, in->regs[0], in);
}
}
}
+static void
+assign_arr_base(struct ir3_ra_ctx *ctx, struct ir3_array *arr,
+ struct ir3_instruction **precolor, unsigned nprecolor)
+{
+ /* In the mergedregs case, we convert full precision arrays
+ * to their effective half-precision base, and find conflicts
+ * amongst all other arrays/inputs.
+ *
+ * In the splitregs case (halfreg file and fullreg file do
+ * not conflict), we ignore arrays and other pre-colors that
+ * are not the same precision.
+ */
+ bool mergedregs = ctx->v->mergedregs;
+ unsigned base = 0;
+
+ /* figure out what else we conflict with which has already
+ * been assigned:
+ */
+retry:
+ foreach_array (arr2, &ctx->ir->array_list) {
+ if (arr2 == arr)
+ break;
+ ra_assert(ctx, arr2->start_ip <= arr2->end_ip);
+
+ unsigned base2 = arr2->reg;
+ unsigned len2 = arr2->length;
+ unsigned len = arr->length;
+
+ if (mergedregs) {
+ /* convert into half-reg space: */
+ if (!arr2->half) {
+ base2 *= 2;
+ len2 *= 2;
+ }
+ if (!arr->half) {
+ len *= 2;
+ }
+ } else if (arr2->half != arr->half) {
+ /* for split-register-file mode, we only conflict with
+ * other arrays of same precision:
+ */
+ continue;
+ }
+
+ /* if it intersects with liverange AND register range.. */
+ if (intersects(arr->start_ip, arr->end_ip,
+ arr2->start_ip, arr2->end_ip) &&
+ intersects(base, base + len,
+ base2, base2 + len2)) {
+ base = MAX2(base, base2 + len2);
+ goto retry;
+ }
+ }
+
+ /* also need to not conflict with any pre-assigned inputs: */
+ for (unsigned i = 0; i < nprecolor; i++) {
+ struct ir3_instruction *instr = precolor[i];
+
+ if (!instr || (instr->flags & IR3_INSTR_UNUSED))
+ continue;
+
+ struct ir3_ra_instr_data *id = &ctx->instrd[instr->ip];
+
+ /* only consider the first component: */
+ if (id->off > 0)
+ continue;
+
+ unsigned name = ra_name(ctx, id);
+ unsigned regid = instr->regs[0]->num;
+ unsigned reglen = class_sizes[id->cls];
+ unsigned len = arr->length;
+
+ if (mergedregs) {
+ /* convert into half-reg space: */
+ if (!is_half(instr)) {
+ regid *= 2;
+ reglen *= 2;
+ }
+ if (!arr->half) {
+ len *= 2;
+ }
+ } else if (is_half(instr) != arr->half) {
+ /* for split-register-file mode, we only conflict with
+ * other arrays of same precision:
+ */
+ continue;
+ }
+
+ /* Check if array intersects with liverange AND register
+ * range of the input:
+ */
+ if (intersects(arr->start_ip, arr->end_ip,
+ ctx->def[name], ctx->use[name]) &&
+ intersects(base, base + len,
+ regid, regid + reglen)) {
+ base = MAX2(base, regid + reglen);
+ goto retry;
+ }
+ }
+
+ /* convert back from half-reg space to fullreg space: */
+ if (mergedregs && !arr->half) {
+ base = DIV_ROUND_UP(base, 2);
+ }
+
+ arr->reg = base;
+}
+
/* handle pre-colored registers. This includes "arrays" (which could be of
* length 1, used for phi webs lowered to registers in nir), as well as
* special shader input values that need to be pinned to certain registers.
static void
ra_precolor(struct ir3_ra_ctx *ctx, struct ir3_instruction **precolor, unsigned nprecolor)
{
- unsigned num_precolor = 0;
for (unsigned i = 0; i < nprecolor; i++) {
if (precolor[i] && !(precolor[i]->flags & IR3_INSTR_UNUSED)) {
struct ir3_instruction *instr = precolor[i];
struct ir3_ra_instr_data *id = &ctx->instrd[instr->ip];
- debug_assert(!(instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH)));
-
- /* only consider the first component: */
- if (id->off > 0)
- continue;
-
- if (ctx->scalar_pass && !should_assign(ctx, instr))
- continue;
+ ra_assert(ctx, !(instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH)));
/* 'base' is in scalar (class 0) but we need to map that
* the conflicting register of the appropriate class (ie.
* .. and so on..
*/
unsigned regid = instr->regs[0]->num;
+ ra_assert(ctx, regid >= id->off);
+ regid -= id->off;
+
unsigned reg = ctx->set->gpr_to_ra_reg[id->cls][regid];
unsigned name = ra_name(ctx, id);
ra_set_node_reg(ctx->g, name, reg);
- num_precolor = MAX2(regid, num_precolor);
}
}
- /* pre-assign array elements:
- *
- * TODO this is going to need some work for half-precision.. possibly
- * this is easier on a6xx, where we can just divide array size by two?
- * But on a5xx and earlier it will need to track two bases.
+ /*
+ * Pre-assign array elements:
*/
foreach_array (arr, &ctx->ir->array_list) {
- unsigned base = 0;
if (arr->end_ip == 0)
continue;
- /* figure out what else we conflict with which has already
- * been assigned:
- */
-retry:
- foreach_array (arr2, &ctx->ir->array_list) {
- if (arr2 == arr)
- break;
- if (arr2->end_ip == 0)
- continue;
- /* if it intersects with liverange AND register range.. */
- if (intersects(arr->start_ip, arr->end_ip,
- arr2->start_ip, arr2->end_ip) &&
- intersects(base, base + reg_size_for_array(arr),
- arr2->reg, arr2->reg + reg_size_for_array(arr2))) {
- base = MAX2(base, arr2->reg + reg_size_for_array(arr2));
- goto retry;
- }
- }
-
- /* also need to not conflict with any pre-assigned inputs: */
- for (unsigned i = 0; i < nprecolor; i++) {
- struct ir3_instruction *instr = precolor[i];
-
- if (!instr || (instr->flags & IR3_INSTR_UNUSED))
- continue;
-
- struct ir3_ra_instr_data *id = &ctx->instrd[instr->ip];
-
- /* only consider the first component: */
- if (id->off > 0)
- continue;
-
- unsigned name = ra_name(ctx, id);
- unsigned regid = instr->regs[0]->num;
-
- /* Check if array intersects with liverange AND register
- * range of the input:
- */
- if (intersects(arr->start_ip, arr->end_ip,
- ctx->def[name], ctx->use[name]) &&
- intersects(base, base + reg_size_for_array(arr),
- regid, regid + class_sizes[id->cls])) {
- base = MAX2(base, regid + class_sizes[id->cls]);
- goto retry;
- }
- }
-
- arr->reg = base;
+ if (!ctx->scalar_pass)
+ assign_arr_base(ctx, arr, precolor, nprecolor);
for (unsigned i = 0; i < arr->length; i++) {
- unsigned name, reg;
-
- if (arr->half) {
- /* Doesn't need to do this on older generations than a6xx,
- * since there's no conflict between full regs and half regs
- * on them.
- *
- * TODO Presumably "base" could start from 0 respectively
- * for half regs of arrays on older generations.
- */
- unsigned base_half = base * 2 + i;
- reg = ctx->set->gpr_to_ra_reg[0+HALF_OFFSET][base_half];
- base = base_half / 2 + 1;
- } else {
- reg = ctx->set->gpr_to_ra_reg[0][base++];
- }
+ unsigned cls = arr->half ? HALF_OFFSET : 0;
- name = arr->base + i;
- ra_set_node_reg(ctx->g, name, reg);
+ ra_set_node_reg(ctx->g,
+ arr->base + i, /* vreg name */
+ ctx->set->gpr_to_ra_reg[cls][arr->reg + i]);
}
}
static void
ra_precolor_assigned(struct ir3_ra_ctx *ctx)
{
- debug_assert(ctx->scalar_pass);
+ ra_assert(ctx, ctx->scalar_pass);
foreach_block (block, &ctx->ir->block_list) {
foreach_instr (instr, &block->instr_list) {
precolor(ctx, instr);
- struct ir3_register *src;
foreach_src (src, instr) {
if (!src->instr)
continue;
debug_assert(dst->num == (src->num + instr->split.off));
} else if (instr->opc == OPC_META_COLLECT) {
struct ir3_register *dst = instr->regs[0];
- struct ir3_register *src;
foreach_src_n (src, n, instr) {
debug_assert(dst->num == (src->num - n));
struct ir3_ra_ctx ctx = {
.v = v,
.ir = v->ir,
- .set = v->ir->compiler->set,
+ .set = v->mergedregs ?
+ v->ir->compiler->mergedregs_set : v->ir->compiler->set,
.scalar_pass = scalar_pass,
};
int ret;
+ ret = setjmp(ctx.jmp_env);
+ if (ret)
+ goto fail;
+
ra_init(&ctx);
ra_add_interference(&ctx);
ra_precolor(&ctx, precolor, nprecolor);
if (scalar_pass)
ra_precolor_assigned(&ctx);
ret = ra_alloc(&ctx);
+
+fail:
ra_destroy(&ctx);
return ret;
if (ret)
return ret;
- if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
- printf("AFTER RA (1st pass):\n");
- ir3_print(v->ir);
- }
+ ir3_debug_print(v->ir, "AFTER: ir3_ra (1st pass)");
/* Second pass, assign the scalar registers: */
ret = ir3_ra_pass(v, precolor, nprecolor, true);
if (ret)
return ret;
- if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
- printf("AFTER RA (2nd pass):\n");
- ir3_print(v->ir);
- }
+ ir3_debug_print(v->ir, "AFTER: ir3_ra (2st pass)");
#ifdef DEBUG
# define SANITY_CHECK DEBUG
projects / mesa.git / blobdiff