freedreno/ir3: Fix disasm of register offsets in ldp/stp.
[mesa.git] / src / freedreno / ir3 / tests / disasm.c
index 3ab1e392cc602bbfe368024e437cd69ce7d99a9f..e6f8f7b28618970f5ddb6b3ca5897c615a68c7d1 100644 (file)
  * IN THE SOFTWARE.
  */
 
+/* Unit test for disassembly of instructions.
+ *
+ * The goal is to take instructions we've seen the blob produce, and test that
+ * we can disassemble them correctly.  For the next person investigating the
+ * behavior of this instruction, please include the testcase it was generated
+ * from, and the qcom disassembly as a comment if it differs from what we
+ * produce.
+ */
+
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include "util/macros.h"
 #include "instr-a3xx.h"
 
+#define INSTR_5XX(i, d) { .gpu_id = 540, .instr = #i, .expected = d }
 #define INSTR_6XX(i, d) { .gpu_id = 630, .instr = #i, .expected = d }
 
 static const struct test {
@@ -71,13 +81,69 @@ static const struct test {
        INSTR_6XX(8010000a_00000003, "rcp r2.z, r0.w"),
 
        /* cat5 */
+       /* dEQP-VK.glsl.derivate.dfdx.uniform_if.float_mediump */
+       INSTR_6XX(a3801102_00000001, "dsx (f32)(x)r0.z, r0.x"), /* dsx (f32)(xOOO)r0.z, r0.x */
+       /* dEQP-VK.glsl.derivate.dfdy.uniform_if.float_mediump */
+       INSTR_6XX(a3c01102_00000001, "dsy (f32)(x)r0.z, r0.x"), /* dsy (f32)(xOOO)r0.z, r0.x */
+       /* dEQP-VK.glsl.derivate.dfdxfine.uniform_loop.float_highp */
+       INSTR_6XX(a6001105_00000001, "dsxpp.1 (x)r1.y, r0.x"), /* dsxpp.1 (xOOO)r1.y, r0.x */
+       INSTR_6XX(a6201105_00000001, "dsxpp.1.p (x)r1.y, r0.x"), /* dsxpp.1 (xOOO)r1.y, r0.x */
+
        INSTR_6XX(a2802f00_00000001, "getsize (u16)(xyzw)hr0.x, r0.x, t#0"),
 
        /* cat6 */
+
        INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x"),
-       INSTR_6XX(c1100000_c1000000, "stl.f16 l[0], hr0.x, hr48.y"),
-       INSTR_6XX(c0260000_0063c200, "resinfo.untyped.2d.u32.1.imm r0.x, r0.x, 0"), /* resinfo.u32.2d.mode0.base0 r0.x, 0 */
-       INSTR_6XX(c0260000_0063c000, "resinfo.untyped.1d.u32.1.imm r0.x, r0.x, 0"), /* resinfo.u32.1d.mode0.base0 r0.x, 0 */
+       /* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
+       INSTR_6XX(c0d20906_02800004, "stg.f32 g[r1.x+r1.z], r0.z, 2"), /* stg.a.f32 g[r1.x+(r1.z<<2)], r0.z, 2 */
+
+       /* TODO: We don't support disasm of stc yet and produce a stgb instead
+        * (same as their disasm does for other families.  They're used as part
+        * uniforms setup, followed by a shpe and then a load of the constant that
+        * was stored in the dynamic part of the shader.
+        */
+       /* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */
+       /* INSTR_6XX(c7020020_01800000, "stc c[32], r0.x, 1"), */
+       /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
+       /* INSTR_6XX(c7060020_03800000, "stc c[32], r0.x, 3"), */
+
+       /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
+       INSTR_6XX(c0260200_03676100, "stib.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
+       /* dEQP-VK.texture.filtering.cube.formats.a8b8g8r8_srgb_nearest_mipmap_nearest.txt */
+       INSTR_6XX(c0220200_0361b801, "ldib.typed.1d.f32.4.imm r0.x, r0.w, 1"), /* ldib.f32.1d.4.mode0.base0 r0.x, r0.w, 1 */
+
+       /* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
+       INSTR_6XX(c2c21100_04800006, "stlw.f32 l[r2.x], r0.w, 4"),
+       INSTR_6XX(c2c20f00_01800004, "stlw.f32 l[r1.w], r0.z, 1"),
+       INSTR_6XX(c2860003_02808011, "ldlw.u32 r0.w, l[r0.z+8], 2"),
+
+       /* dEQP-VK.compute.basic.shared_var_single_group */
+       INSTR_6XX(c1060500_01800008, "stl.u32 l[r0.z], r1.x, 1"),
+       INSTR_6XX(c0460001_01804001, "ldl.u32 r0.y, l[r0.y], 1"),
+
+       /* resinfo */
+       INSTR_6XX(c0260000_0063c200, "resinfo.untyped.2d.u32.1.imm r0.x, 0"), /* resinfo.u32.2d.mode0.base0 r0.x, 0 */
+       /* dEQP-GLES31.functional.image_load_store.buffer.image_size.writeonly_7.txt */
+       INSTR_6XX(c0260000_0063c000, "resinfo.untyped.1d.u32.1.imm r0.x, 0"), /* resinfo.u32.1d.mode0.base0 r0.x, 0 */
+       /* dEQP-VK.image.image_size.2d.readonly_12x34.txt */
+       INSTR_6XX(c0260000_0063c300, "resinfo.untyped.2d.u32.1.imm.base0 r0.x, 0"), /* resinfo.u32.2d.mode4.base0 r0.x, 0 */
+       /* dEQP-GLES31.functional.image_load_store.buffer.image_size.readonly_writeonly_7 */
+       INSTR_5XX(c3e60000_00000e00, "resinfo.4d r0.x, g[0]"), /* resinfo.u32.1dtype r0.x, 0 */
+       /* dEQP-GLES31.functional.image_load_store.2d.image_size.readonly_writeonly_32x32.txt */
+       INSTR_5XX(c3e60000_00000200, "resinfo.2d r0.x, g[0]"), /* resinfo.u32.2d r0.x, 0 */
+       /* dEQP-GLES31.functional.image_load_store.3d.image_size.readonly_writeonly_12x34x56 */
+       INSTR_5XX(c3e60000_00000c00, "resinfo.3d r0.x, g[0]"), /* resinfo.u32.3d r0.x, 0 */
+
+       /* ldgb */
+       /* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_vec4 */
+       INSTR_5XX(c6e20000_06003600, "ldgb.untyped.4d.f32.4 r0.x, g[0], r0.x, r1.z"), /* ldgb.a.untyped.1dtype.f32.4 r0.x, g[r0.x], r1.z, 0 */
+       /* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_ivec4 */
+       INSTR_5XX(c6ea0000_06003600, "ldgb.untyped.4d.s32.4 r0.x, g[0], r0.x, r1.z"), /* ldgb.a.untyped.1dtype.s32.4 r0.x, g[r0.x], r1.z, 0 */
+       /* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_float */
+       INSTR_5XX(c6e20000_02000600, "ldgb.untyped.4d.f32.1 r0.x, g[0], r0.x, r0.z"), /* ldgb.a.untyped.1dtype.f32.1 r0.x, g[r0.x], r0.z, 0 */
+       /* dEQP-GLES31.functional.ssbo.layout.random.vector_types.0 */
+       INSTR_5XX(c6ea0008_14002600, "ldgb.untyped.4d.s32.3 r2.x, g[0], r0.x, r5.x"), /* ldgb.a.untyped.1dtype.s32.3 r2.x, g[r0.x], r5.x, 0 */
+       INSTR_5XX(c6ea0204_1401a600, "ldgb.untyped.4d.s32.3 r1.x, g[1], r1.z, r5.x"), /* ldgb.a.untyped.1dtype.s32.3 r1.x, g[r1.z], r5.x, 1 */
 
        /* discard stuff */
        INSTR_6XX(42b400f8_20010004, "cmps.s.eq p0.x, r1.x, 1"),
@@ -112,6 +178,14 @@ static const struct test {
        INSTR_6XX(c0260000_00478400, "ldc.offset2.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
        INSTR_6XX(c0260000_00478600, "ldc.offset3.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
 
+       /* dEQP-VK.glsl.struct.local.nested_struct_array_dynamic_index_fragment */
+       INSTR_6XX(c1425b50_01803e02, "stp.f32 p[r11.y-176], r0.y, 1"),
+       INSTR_6XX(c1425b98_02803e14, "stp.f32 p[r11.y-104], r2.z, 2"),
+       INSTR_6XX(c1465ba0_01803e2a, "stp.u32 p[r11.y-96], r5.y, 1"),
+       INSTR_6XX(c0860008_01860001, "ldp.u32 r2.x, p[r6.x], 1"),
+       /* Custom stp based on above to catch a disasm bug. */
+       INSTR_6XX(c1465b00_0180022a, "stp.u32 p[r11.y+256], r5.y, 1"),
+
        /* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d */
        INSTR_6XX(a0c01f04_0cc00005, "sam (f32)(xyzw)r1.x, r0.z, s#6, t#6"),
        /* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.fragment.sampler2d (looks like maybe the compiler didn't figure out */