freedreno/a6xx: Implement PIPE_QUERY_PRIMITIVES_GENERATED for GS

[mesa.git] / src / freedreno / registers / a6xx.xml

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 4d83a5dd2cfd69f5631db1ce83c00126ff6669f7..b7cfecdc121787697ac12957e5c1fce8cd4d50ee 100644 (file)
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1372,6 +1372,38 @@ to upconvert to 32b float internally?
        <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
        <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
        <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
+
+       <!---
+           This block of registers aren't tied to perf counters. They
+           count various geometry stats, for example number of
+           vertices in, number of primnitives assembled etc.
+       -->
+
+       <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>
+       <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
+       <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>
+       <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
+       <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>
+       <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
+       <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>
+       <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
+       <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>
+       <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
+       <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>
+       <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
+       <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>
+       <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
+       <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>
+       <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
+       <!-- PRIMCTR_8 appears to count number of primitives coming out of GS -->
+       <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>
+       <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
+       <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>
+       <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
+       <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
+       <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
+       
+
        <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
        <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
        <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>