freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.

[mesa.git] / src / freedreno / registers / adreno / a6xx.xml

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 63653c2fb4547040602f186f45a3c22f111a8203..15314fbb7365c15ced9a219a9e590ead9cdc777a 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -3325,7 +3325,17 @@ to upconvert to 32b float internally?
        <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
 
        <!-- always 0x5 ? -->
-       <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
+       <reg32 offset="0xab00" name="SP_MODE_CONTROL">
+         <!--
+         When set, half register loads from the constant file will
+         load a 32-bit value (so hc0.y loads the same value as c0.y)
+         and implicitly convert it to 16b (f2f16, or u2u16, based on
+         operand type).  When unset, half register loads from the
+         constant file will load 16 bits from the packed constant
+         file (so hc0.y loads the top 16 bits of the value of c0.x)
+         -->
+               <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
+       </reg32>
 
        <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
        <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>