int msm_major_version;
int msm_minor_version;
+ bool limited_z24s8;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
volatile uint32_t vsc_draw_overflow;
uint32_t _pad1;
volatile uint32_t vsc_prim_overflow;
- uint32_t _pad2[3];
+ uint32_t _pad2;
+ uint64_t predicate;
/* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
struct {
struct tu_cs_entry tile_store_ib;
bool xfb_used;
+ bool has_tess;
+ bool has_subpass_predication;
+ bool predication_active;
};
struct tu_cmd_pool
struct tu_cs draw_epilogue_cs;
struct tu_cs sub_cs;
- bool has_tess;
-
uint32_t vsc_draw_strm_pitch;
uint32_t vsc_prim_strm_pitch;
};
const struct ir3_shader_variant *hs,
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
- const struct ir3_shader_variant *fs);
+ const struct ir3_shader_variant *fs,
+ uint32_t patch_control_points,
+ bool vshs_workgroup);
void
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
uint32_t RB_2D_DST_INFO;
uint32_t RB_BLIT_DST_INFO;
+
+ /* for d32s8 separate stencil */
+ uint64_t stencil_base_addr;
+ uint32_t stencil_layer_size;
+ uint32_t stencil_PITCH;
};
struct tu_sampler_ycbcr_conversion {
void
tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
+void
+tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
+
+#define tu_image_view_stencil(iview, x) \
+ ((iview->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
+
VkResult
tu_image_create(VkDevice _device,
const VkImageCreateInfo *pCreateInfo,
VkImage *out_image_h);
void
-tu_image_view_init(struct tu_image_view *view,
- const VkImageViewCreateInfo *pCreateInfo);
+tu_image_view_init(struct tu_image_view *iview,
+ const VkImageViewCreateInfo *pCreateInfo,
+ bool limited_z24s8);
struct tu_buffer_view
{
bool load;
bool store;
int32_t gmem_offset;
+ /* for D32S8 separate stencil: */
+ bool load_stencil;
+ bool store_stencil;
+ int32_t gmem_offset_stencil;
};
struct tu_render_pass
VkDescriptorUpdateTemplate descriptorUpdateTemplate,
const void *pData);
-int
-tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
-
-int
-tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
-
-int
-tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
+VkResult
+tu_physical_device_init(struct tu_physical_device *device,
+ struct tu_instance *instance);
+VkResult
+tu_enumerate_devices(struct tu_instance *instance);
int
tu_drm_submitqueue_new(const struct tu_device *dev,
void
tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
-uint32_t
-tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
-uint32_t
-tu_gem_import_dmabuf(const struct tu_device *dev,
- int prime_fd,
- uint64_t size);
-int
-tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
-void
-tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
-uint64_t
-tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
-uint64_t
-tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
-
#define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
\
static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \