gallivm/nir: add indirect swizzle output loading support

[mesa.git] / src / gallium / auxiliary / gallivm / lp_bld_tgsi_soa.c

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 5104a572c4dc78ba2274817e2cee1af09fef60e9..cbaebca48812eb91feceab48b832f22ee9bd06e6 100644 (file)
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1255,6 +1255,7 @@ emit_fetch_tcs_input(
                                               vertex_index,
                                               reg->Register.Indirect,
                                               attrib_index,
+                                              FALSE,
                                               swizzle_index,
                                               bld_base->info->output_semantic_name[reg->Register.Index]);
    } else {
@@ -1263,6 +1264,7 @@ emit_fetch_tcs_input(
                                              vertex_index,
                                              reg->Register.Indirect,
                                              attrib_index,
+                                             FALSE,
                                              swizzle_index);
    }
 
@@ -1277,6 +1279,7 @@ emit_fetch_tcs_input(
                                                   vertex_index,
                                                   reg->Register.Indirect,
                                                   attrib_index,
+                                                  FALSE,
                                                   swizzle_index,
                                                   bld_base->info->output_semantic_name[reg->Register.Index]);
       } else {
@@ -1285,6 +1288,7 @@ emit_fetch_tcs_input(
                                                  vertex_index,
                                                  reg->Register.Indirect,
                                                  attrib_index,
+                                                 FALSE,
                                                  swizzle_index);
       }
       assert(res2);
@@ -1358,6 +1362,7 @@ emit_fetch_tes_input(
                                        vertex_index,
                                        reg->Register.Indirect,
                                        attrib_index,
+                                       FALSE,
                                        swizzle_index);
    }
 
@@ -1377,6 +1382,7 @@ emit_fetch_tes_input(
                                              vertex_index,
                                              reg->Register.Indirect,
                                              attrib_index,
+                                             FALSE,
                                              swizzle_index);
       }
       assert(res2);